Interface Card Cache Control for Storage Processor Offload

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Solution Overview

Problem

In storage systems, frequent data access by a host to a storage subsystem strains the processing resources of the storage device, reducing the processing rate for other events and the access rate to the storage subsystem.

Innovation Solution

A data access method and apparatus that utilize a cache control unit, interface card, and cache to manage data write and read operations without consuming processor resources, by generating and sending instructions directly from the interface card to the storage subsystem, allowing the cache to handle data processing and storage operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the processor of the storage device handles data access requests from the host, then the data access function is provided, but the processing resources of the processor are strained and the processing rate for other events is reduced

Engineering Contradiction:
Improvedata access functionVSAvoidprocessing rate for other events
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent extracts the data access processing function from the main processor by introducing a dedicated interface card with its own processor. The interface card independently handles data read/write requests between the host and storage subsystem, removing this workload from the main processor and freeing its processing resources for other events.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The interface card acts as an intermediary component between the host and the storage subsystem. It receives data access requests from the host, processes them independently using its own processor, and communicates with the storage subsystem without involving the main processor, thus mediating the data access function and protecting the main processor's resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the processor handles frequent data access requests, then the host can access the storage subsystem, but the access rate to the storage subsystem is reduced

Engineering Contradiction:
Improveaccess rate to storage subsystemVSAvoidprocessing time for data access
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the data access processing function from the main processor by introducing a dedicated interface card with its own processor. The interface card independently handles data read/write requests between the host and storage subsystem, removing this workload from the main processor and freeing its processing resources for other events.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The interface card is pre-configured with the capability to handle data access requests independently. By having the processing function already extracted and assigned to the interface card before operation, the system eliminates the need for the main processor to intervene in routine data access operations, thereby reducing access time and improving throughput.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11144465B2Data access method and apparatus
Publication Date: 2021.10.12 HUAWEI TECH CO LTD
  • US11144465B2 patent drawing
  • US11144465B2 patent drawing
  • US11144465B2 patent drawing

AI summary

In a data access method, after an interface card receives a first data write instruction or a first data read instruction, the interface card generates a second data write instruction or a second data read instruction, and writes the second data write instruction or the second data read instruction into a cache. No resource of a processor of a storage device is used. After the interface card writes the second data write instruction or the second data read instruction into the cache, a cache control unit sends the second data write instruction or the second data read instruction to a storage subsystem. No resource of the processor of the storage device is used. Alternatively, the cache control unit may instruct the storage subsystem to execute the second data write instruction or the second data read instruction.