Interface Cell Power Supply Line Structure for IC Area Reduction
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Solution Overview
Problem
The size reduction of integrated circuits is limited by the large area requirements of the power supply line structure due to current carrying constraints, particularly for electrostatic discharge (ESD) protection, which restricts the miniaturization of interface cells in integrated circuits.
Innovation Solution
The power supply line section within each interface cell includes a first supply line portion sized to support current carrying constraints and a second supply line portion that is insufficient on its own but connected to an external current carrying structure, allowing the combination to meet the current carrying requirements while reducing the overall area of the power supply line structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power supply line structure is sized to support current carrying constraints during ESD events, then the current carrying capability is improved, but the area occupied by the power supply line structure increases
Solution Approach 1:
The patent transitions from a two-dimensional planar power supply line structure to a three-dimensional structure by utilizing vertical vias to connect different metal layers. This allows the power supply lines to extend through multiple layers, increasing current carrying capability without proportionally increasing the lateral area occupied on the chip surface.
Solution Approach 2:
The patent employs a composite power supply line structure combining multiple metal layers with different thicknesses and materials. Thicker metal layers are used in regions requiring higher current carrying capability, while thinner layers are used where less current is needed, optimizing the balance between area and current capacity.
2Object-affected harmful factors
If the power supply line structure is made larger to meet current carrying requirements, then the ESD protection capability is improved, but the size of interface cells increases
Solution Approach 1:
The patent uses multiple metal layers stacked vertically to provide sufficient current carrying paths for ESD events. By distributing the current path across multiple layers connected via vias, the lateral area required in each individual layer is reduced, allowing smaller interface cell footprints while maintaining robust ESD protection.
Solution Approach 2:
The power supply line structure is segmented into multiple sections across different metal layers. Each layer contributes a portion of the total current carrying capability, and the segments are connected through vias. This segmentation allows the ESD current to be distributed across multiple parallel paths, reducing the area burden on any single interface cell.
3Area of stationary object
If the power supply line structure is reduced in size to minimize interface cell area, then the area of interface circuitry is reduced, but the current carrying constraint cannot be met
Solution Approach 1:
The patent compensates for reduced lateral dimensions by exploiting the vertical dimension through multiple metal layers. The power supply lines are configured to utilize available space in the vertical stacking of layers, maintaining sufficient cross-sectional area for current flow even when the lateral footprint is minimized for compact interface cells.
Solution Approach 2:
The patent merges multiple thin power supply line sections from different metal layers into a unified three-dimensional power supply structure. By combining the current carrying capacity of multiple layers through via connections, the overall current carrying capability equals or exceeds that of a single large planar structure, while occupying less lateral area.
Data Source
AI summary
An integrated circuit is provided with interface circuitry used to provide an interface between functional circuitry of the integrated circuit and components external to the integrated circuit. The interface circuitry includes a plurality of interface cells having interface components configured to operate from a first power supply. Each interface cell incorporates a power supply line section extending across its width and configured to cooperate with power supply line sections of other interface cells to provide a power supply line structure shared by the plurality of interface cells, for provision of the first power supply to the interface components. Each power supply line section includes a first supply line portion and a second supply line portion, the first supply line portion being sized to support a current carrying constraint of the interface circuitry, while the second supply line portion is sized insufficiently to support that current carrying constraint. Instead, each interface cell is arranged within the interface circuitry such that the second supply line portion is connected to a current carrying structure external to that interface cell, such that the second supply line portion in combination with the connected current carrying structure is sized sufficiently to support the current carrying constraint. Such an approach enables a reduction in the area required for the power supply line structure, hence enabling a reduction in the size of the interface circuitry, and accordingly a corresponding reduction in the required size of the integrated circuit.