Interface Chip Built-In Self-Test Loopback Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional automatic test equipment for interface chips is complex and expensive due to the high data rates of interface chips, particularly for high-speed interfaces like USB 3.0 and USB 3.1, necessitating a more efficient testing method.
Innovation Solution
A built-in self-test technology for interface chips using a loopback test circuit with a scrambler, equalizer, and descrambler, which generates a test sequence with a synchronization section and repeated test code, scrambles and descrambles signals to verify chip functionality without external test boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional automatic test equipment is used to test interface chips, then testing can be performed, but the test equipment becomes very complex and expensive due to high data rates
Solution Approach 1:
The interface chip performs self-testing by generating test sequences internally and using its own receiver to detect them. The transmitter generates a test sequence, scrambles it, transmits it through the loopback path, and the receiver detects and descrambles it. This self-service approach eliminates the need for complex external test equipment while maintaining reliable testing capability.
Solution Approach 2:
The test function is nested within the interface chip itself rather than being implemented externally. The test sequence generator, scrambler, equalizer, and descrambler are all integrated within the chip, creating a nested structure where the testing mechanism is contained within the object being tested.
2Measurement precision
If high-speed interface chips are tested with conventional ATE, then signal accuracy can be checked, but the cost increases significantly
Solution Approach 1:
The interface chip uses its own internal resources to perform accurate signal measurement. The receiver detects the transmitted signal and the descrambler recovers the original test sequence, enabling precise signal accuracy checking without external equipment. The equalizer optimizes signal quality before detection, ensuring measurement precision.
Solution Approach 2:
The test sequence is generated as a digital copy within the chip and processed through the same transmission and reception paths as actual data. This digital copying approach allows accurate signal measurement using internal digital logic rather than expensive analog test equipment.
3Reliability
If external test boards are used for interface chip testing, then comprehensive testing can be performed, but the solution becomes less cost-effective
Solution Approach 1:
The interface chip performs comprehensive functionality assessment on its own by generating test sequences, processing them through all transmission and reception stages, and verifying the results internally. The loopback test circuit connects the transmitter output to the receiver input, creating a self-contained testing system that eliminates external test boards.
Solution Approach 2:
The testing function is merged with the normal operation of the interface chip. The same transmitter, scrambler, equalizer, and descrambler used for data communication are utilized for testing, combining these functions into a single integrated system rather than requiring separate external test equipment.
Data Source
AI summary
A built-in self-test mechanism for an interface chip. During a loopback test procedure, a transmission terminal of the interface chip is coupled back to the interface chip by a reception terminal of the interface chip and a loopback test circuit within the interface chip generates a test sequence which includes a synchronization section and a section of repeated test code. The test sequence is scrambled by a scrambler and then is transmitted via the transmission terminal and looped back to the reception terminal. The signal looped back to the reception terminal is processed by an equalizer and descrambled by a descrambler to be further checked by the loopback test circuit for determining whether the interface chip is functioning normally. The dynamically-changed keys used in the scrambler and the descrambler are synchronized according to the synchronization section. The equalizer is optimized by the scrambled section of repeated test code.