Memory Interface Chip Delay Circuit for Data-Clock Phase Skew
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Solution Overview
Problem
Existing memory packages face reliability issues due to phase skew between data signals and clock signals, which can lead to misalignment and errors, especially as data rates increase, and this skew is difficult to address without separate training times or additional components.
Innovation Solution
A memory package design that includes an interface chip with a delay circuit and sampler, which applies an offset delay and additional delay to the clock signal to align it with the data signal, effectively removing phase skew by adjusting the delay codes based on detected phase differences, allowing accurate sampling and operation without separate training times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased to improve communication speed, then productivity is improved, but phase skew between data signal and clock signal increases causing reliability deterioration
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism where the delay applied to the clock signal is not fixed but is instead adjusted based on the detected phase difference between the data signal and clock signal. The delay circuit modifies the clock signal delay in real-time during training operations to achieve optimal alignment, allowing the system to adapt to varying phase skew conditions that occur at different data rates.
Solution Approach 2:
The patent employs a feedback mechanism where the phase difference between the data signal and clock signal is continuously detected and used to adjust the delay circuit parameters. The training operation measures the actual phase skew and feeds this information back to the delay circuit, which then adjusts the clock signal delay accordingly to minimize phase difference and eliminate sampling errors.
2Reliability
If separate training time is added to remove phase skew, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent performs phase alignment adjustments during the training operation phase, which occurs before normal data transfer operations begin. By completing the delay calibration and phase skew removal during this preliminary training period, the system establishes optimal timing parameters in advance, ensuring reliable data transfer without requiring additional training time during subsequent operations.
3Reliability
If delay circuit with adjustable delay is implemented to remove phase skew, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component between the clock signal source and the sampler. This delay circuit acts as a mediator that adjusts the timing of the clock signal to match the data signal phase. By placing this adjustment mechanism at the interface chip level, the patent localizes the complexity to a specific component rather than requiring system-wide changes, making the solution more manageable and implementable.
Data Source
AI summary
A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.