Interface Chip for NRZ-to-PAM Memory Test Compatibility

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Solution Overview

Problem

Memory devices face compatibility issues during testing due to differences in signaling methods between test devices and devices under test, leading to inefficiencies in input/output interfaces.

Innovation Solution

An interface chip with first and second interface circuits for NRZ and PAM signals, respectively, and a conversion circuit to adapt signals between these formats, enabling bidirectional communication and supporting different data rates and modulation schemes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a test device uses a specific signaling method (NRZ) to test a memory device, then the test device can operate with its existing interface, but compatibility issues arise when the memory device uses a different signaling method (PAM)

Engineering Contradiction:
Improvesignal format compatibilityVSAvoidinterface conversion complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an interface chip as an intermediary device between the test device and the memory device. This interface chip includes a first interface circuit that communicates with the test device using NRZ signaling and a second interface circuit that communicates with the memory device using PAM signaling. The conversion circuit within the interface chip performs the signal format conversion, allowing the test device and memory device to communicate despite using different signaling methods, thereby resolving the compatibility issue without requiring changes to either the test device or the memory device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conversion circuit changes the signal parameters by transforming NRZ signals into PAM signals and vice versa. This parameter transformation enables the interface chip to adapt between different signaling methods, allowing the test system to work with memory devices that use different signaling standards without requiring multiple specialized test devices.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If multiple test devices are used to support different signaling methods (NRZ and PAM), then compatibility with various memory devices is improved, but equipment investment and system complexity increase

Engineering Contradiction:
Improvesupport for multiple signaling methodsVSAvoidnumber of test devices
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The interface chip is designed with multi-functionality to handle both NRZ and PAM signaling methods. By integrating both interface circuits (first for NRZ, second for PAM) and the conversion circuit within a single chip, the system achieves universal compatibility with different memory device signaling standards. This eliminates the need to acquire separate test devices for different signaling methods, reducing equipment investment while maintaining adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If signal conversion is performed between NRZ and PAM formats, then compatibility between test device and memory device is enhanced, but conversion circuit complexity increases

Engineering Contradiction:
Improvesignal format conversion capabilityVSAvoidconversion circuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the NRZ interface circuit, PAM interface circuit, and conversion circuit into a single integrated interface chip. This consolidation achieves signal format conversion capability while avoiding the complexity of having separate conversion devices. The integrated design allows the conversion functionality to be embedded within the chip's internal architecture, reducing overall system complexity despite the inherent complexity of the conversion operations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20260057958A1Interface chip and test system including the same
Publication Date: 2026.02.26 SAMSUNG ELECTRONICS CO LTD
  • US20260057958A1 patent drawing
  • US20260057958A1 patent drawing
  • US20260057958A1 patent drawing

AI summary

An interface chip includes a first interface circuit connected to a test device, the first interface circuit providing an interface for a first non-return to zero (NRZ) signal and a sideband signal for the test device; a second interface circuit connected to a device under test (DUT), the second interface circuit providing an interface for a second NRZ signal and a pulse amplitude modulation (PAM) signal for the DUT; and a conversion circuit connected to the first interface circuit and the second interface circuit, the conversion circuit providing conversion between the first NRZ signal and the second NRZ signal and between the first NRZ signal and the PAM signal based on the sideband signal.