Hierarchical Interface Chip Architecture for NV Memory Control
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Solution Overview
Problem
Conventional SSD controller architectures face challenges in balancing high performance and reliability, particularly when increasing storage capacity, leading to tradeoffs between performance and reliability, and requiring additional heat dissipation mechanisms that occupy space.
Innovation Solution
A storage device and interface chip architecture featuring a hierarchical structure with slave and master interface circuits, and a control circuit that manages operations between memory controllers and NV memory chips, enabling efficient data access and multi-layer data protection to reduce uncorrectable bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of flash memory chips is increased to increase storage capacity, then storage capacity is improved, but controller throughput capability is exceeded and performance deteriorates
Solution Approach 1:
The patent divides the controller into multiple independent interface chips, where each interface chip manages a subset of flash memory chips. This segmentation allows parallel processing of data operations, enabling the system to handle increased storage capacity without overwhelming a single controller's throughput capability. Each interface chip operates independently to manage its assigned flash memory chips, distributing the processing load across multiple units.
Solution Approach 2:
The patent introduces a hierarchical control architecture that adds a new dimension to the controller-flash memory interface. Instead of a flat one-to-many relationship, the system implements a two-level hierarchy: memory controllers at the top level and interface chips at the intermediate level, each managing specific flash memory chips. This dimensional change enables scalable architecture where storage capacity can be increased by adding more interface chips and flash memory chips without proportionally increasing the burden on individual memory controllers.
2Reliability
If additional data protection calculations are implemented to improve reliability, then reliability is improved, but calculation complexity increases and temperature rises
Solution Approach 1:
The patent distributes data protection calculation functions across multiple interface chips rather than concentrating them in a single memory controller. Each interface chip performs error correction and data protection operations for its assigned flash memory chips independently. This segmentation reduces the computational burden and heat generation at any single point, while collectively maintaining or improving overall system reliability through distributed redundancy and error correction.
3Temperature
If heat dissipation mechanisms are added to manage temperature, then temperature control is improved, but device complexity and space occupation increase
Solution Approach 1:
The patent extracts the data protection calculation functions from the central memory controller and relocates them to distributed interface chips. This extraction reduces the computational workload and heat generation at the memory controller, eliminating or reducing the need for aggressive heat dissipation mechanisms. The thermal management burden is distributed across multiple interface chips that generate less concentrated heat, simplifying the overall thermal management architecture.
4Device complexity
If conventional controller architecture is used to maintain simplicity, then device complexity is reduced, but performance and reliability cannot be ensured simultaneously
Solution Approach 1:
The patent segments the controller into multiple interface chips with standardized, simple interfaces, maintaining architectural simplicity at the interface level while enabling complex parallel operations internally. Each interface chip follows a uniform design pattern, making the system easy to manufacture and understand, yet the collective system delivers enhanced performance and reliability through parallel processing and distributed error correction.
Data Source
AI summary
A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.