Interface Circuit Multilevel Signaling Bandwidth
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Solution Overview
Problem
Current interface circuits for high-speed communication in electronic devices face challenges in increasing bandwidth and reducing power consumption, particularly in supporting new serial communication schemes.
Innovation Solution
The proposed solution involves an interface circuit with a transmitter that drives multiple wire buses using multilevel symbols, where each wire bus is driven to specific voltage levels (high, middle, or low) to transmit balanced code multilevel signals, and includes a termination voltage level to optimize communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional serial communication schemes are used, then device complexity is reduced, but bandwidth is limited and power consumption increases
Solution Approach 1:
The patent applies parameter changes by transitioning from traditional binary signaling to multilevel signaling, where signal voltage levels are changed to represent multiple bits simultaneously. The interface circuit uses differential signaling with multiple voltage levels (e.g., SV, SV-DV, SV-LV, SV-DLV) to encode data, thereby increasing bandwidth without proportionally increasing physical layer complexity
Solution Approach 2:
The patent introduces another dimension by using balanced code multilevel signaling that combines amplitude modulation with differential encoding. This creates an additional signaling dimension beyond simple voltage presence/absence, allowing more data to be transmitted per symbol period while maintaining signal integrity through balanced differential pairs
2Productivity
If communication speed is increased, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action through clocked differential signaling where balanced code multilevel symbols are transmitted in synchronized periods. The interface circuit uses periodic clock signals to control the transmission of differential pairs, allowing high-speed communication while enabling power management techniques that can reduce power during idle or low-activity periods
Solution Approach 2:
The patent changes signal parameters by using multilevel voltage transitions instead of simple binary switching. By transitioning between multiple voltage levels (SV, SV-DV, SV-LV, SV-DLV) in a controlled manner, the circuit achieves higher communication speeds while the balanced differential architecture maintains power efficiency through symmetric signal swings that cancel electromagnetic interference
3Quantity of substance
If balanced code multilevel signaling is used, then bandwidth increases, but signal transmission complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the data stream into balanced code multilevel symbols that are transmitted through separate differential wire pairs. Each differential pair carries segmented portions of the overall data, and the receiver reconstructs the complete signal by combining these segmented transmissions, thereby managing complexity through modular signal processing
Solution Approach 2:
The patent uses differential signaling as an intermediary mechanism that simplifies the transmission of complex multilevel signals. By encoding data in differential voltage differences rather than absolute voltage levels, the system handles signal integrity issues (noise, interference, distortion) more gracefully, reducing the complexity of error correction and signal recovery
Data Source
AI summary
A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.