Interface Circuit Multiplexing Ethernet Signals Over HDMI Lines

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Solution Overview

Problem

Ethernet connections for AV devices lack real-time characteristics due to software processing delays and require large buffers for speed adjustment, leading to jitter and signal delay when transmitting digital signals.

Innovation Solution

An interface circuit that multiplexes differential and common-mode signals, including a clock component, over the same transmission line using reserved and hot-plug detect lines within an HDMI cable, enabling bidirectional communication according to Internet Protocol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If Ethernet is used for connection between AV devices, then bidirectional communication according to IP protocol is achieved, but software processing takes time and real-time characteristics are lost

Engineering Contradiction:
Improvebidirectional communication capabilityVSAvoidreal-time characteristics
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the communication functions by separating audio/video data transmission from control signal transmission. The TMDS channels handle high-speed audio/video data with real-time characteristics, while the Ethernet channel handles control signals and IP protocol communication. This segmentation allows each channel to be optimized for its specific function, preserving real-time characteristics for audio/video while enabling versatile IP communication for control.

Inventive Principle:
Principle #1Segmentation

2Reliability

If synchronization is performed between AV devices to overcome real-time issues, then real-time characteristics can be maintained, but large buffers are required for speed adjustment

Engineering Contradiction:
Improvereal-time characteristicsVSAvoidbuffer size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the clock signal transmission from the data transmission path. By dedicating separate TMDS clock channels to carry clock signals independently, the system can maintain real-time synchronization without requiring large buffers for speed adjustment. The receiver uses these extracted clock signals to synchronize its operations, eliminating the need for extensive buffering while maintaining real-time characteristics.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If a time stamp process is used to send timing information from transmitter to receiver, then clock synchronization can be achieved, but jitter and signal delay occur

Engineering Contradiction:
Improveclock synchronizationVSAvoidsignal delay and jitter
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by transmitting clock signals continuously and independently through dedicated TMDS clock channels before and during data transmission. Instead of using time stamps that are processed after data arrival, the system preliminarily establishes synchronized timing through continuous clock signal transmission, allowing the receiver to maintain accurate timing without experiencing jitter or delay associated with post-processing time stamp regeneration.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10033553B2Interface circuit for transmitting and receiving digital signals between devices
Publication Date: 2018.07.24 SONY GROUP CORP
  • US10033553B2 patent drawing
  • US10033553B2 patent drawing
  • US10033553B2 patent drawing

AI summary

A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.