Interface Circuit Shared Terminals Differential Signal Stability
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Solution Overview
Problem
In systems supporting both single-ended and differential signal methods, the differential signal receiving circuit may inadvertently become inactive at unexpected timings due to transmission errors, leading to communication disruptions.
Innovation Solution
The interface circuit maintains the differential signal receiver in an active state through an enable signal, ensuring it remains active even during garbled bit occurrences, by using dedicated input terminals for differential signals and shared terminals for single-ended signals, with a link controller controlling the active state of the differential signal receiving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the differential signal receiving circuit is controlled to be inactive to reduce power consumption, then electric power consumption is reduced, but the circuit may inadvertently become inactive at unexpected timings due to transmission errors
Solution Approach 1:
A detection circuit is introduced as an intermediary between the transmission path and the differential signal receiving circuit. This detection circuit monitors the differential signal and only activates the receiving circuit when a valid signal is detected, preventing spurious signals from inadvertently activating the receiver while still allowing proper signals to function normally
Solution Approach 2:
The detection circuit automatically detects the presence of valid differential signals and controls the activation state of the receiving circuit without external intervention. The system self-regulates by monitoring its own input signals and adjusting the receiving circuit state accordingly, eliminating the need for external control signals
2Reliability
If the differential signal receiving circuit remains constantly active to ensure reliable reception, then communication stability is improved, but electric power consumption increases
Solution Approach 1:
Instead of continuous operation, the differential signal receiving circuit operates periodically based on detection circuit output. The receiver is activated only during periods when valid signals are detected and deactivated during periods without valid signals, creating an on-demand operation pattern that reduces overall power consumption while maintaining reliability during active periods
3Quantity of substance
If shared signal wires are used for both single-ended and differential signals to reduce wire count, then the number of signal wires is reduced, but transmission errors may occur causing garbled bits
Solution Approach 1:
The detection circuit performs preliminary detection of the differential signal before it reaches the receiving circuit. By detecting the signal characteristics in advance, the system can determine whether to activate the receiving circuit, preventing garbled bits from being processed as valid data and thereby maintaining transmission accuracy despite shared wire usage
Data Source
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AI summary
To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal. A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller. Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.