Interface Circuit for High-Speed Signal Level Conversion

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Solution Overview

Problem

Conventional interface circuits for wireless communication systems, such as GPS receivers, face challenges in achieving high-speed signal level conversion with low power consumption due to through current flow issues when switching between saturated and shutoff states, which hinders sensitivity and size reduction.

Innovation Solution

The interface circuit employs a controller to manage the base voltage of output transistors, ensuring smooth switching between saturated and shutoff states, and utilizes current amplification to reduce the required current for circuit operation, thereby achieving high sensitivity and speed with low power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional bipolar interface circuit is used for signal level conversion, then the circuit can convert ECL level signals to CMOS level signals, but through current flows during transistor switching which increases power consumption and reduces switching speed

Engineering Contradiction:
Improvesignal level conversion speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by pre-charging the base of the PNP transistor through a dedicated current path before the main switching action occurs. This ensures the transistor is ready to switch immediately when the input signal changes, eliminating the through current problem that occurs when the transistor switches from saturated to shutoff state. The base voltage is prepared in advance to prevent delayed switching and through current flow.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary current path that supplies base current to the PNP transistor independently from the main signal path. This intermediary current source (implemented through resistors and transistors) acts as a mediator to maintain proper base voltage during switching transitions, preventing the direct conflict between the input signal and the transistor's switching requirements that causes through current.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If a large current is supplied to the input stage to charge the capacitive load quickly, then high-speed signal processing is achieved, but the current consumption of the entire circuit increases

Engineering Contradiction:
Improvesignal processing speedVSAvoidcurrent consumption
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent segments the current supply function into multiple independent paths: a main signal path and a dedicated base current supply path. This segmentation allows the base current to be supplied through a low-impedance path independent of the signal amplitude, enabling fast switching without requiring large currents from the signal source. The capacitive load is charged through the amplified collector current rather than the base current.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the impedance parameter of the base current supply path to be very low, allowing sufficient base current to flow without significant voltage drop. This parameter change enables the transistor to switch rapidly in response to small input signal changes, achieving high-speed operation with minimal input current while the output stage provides the necessary current for charging the capacitive load.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7327164B2Interface circuit
Publication Date: 2008.02.05 RENESAS ELECTRONICS CORP
  • US7327164B2 patent drawing
  • US7327164B2 patent drawing
  • US7327164B2 patent drawing

AI summary

An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.