Interface Circuit Synthesis for Data Transfer Optimization
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Solution Overview
Problem
Current design tools lack effective support for designing interface circuits between circuit modules, leading to performance bottlenecks and increased circuit area, as they either require labor-intensive manual design or limited customization with standard systems.
Innovation Solution
An information processing device that automatically synthesizes an interface circuit using high-level synthesis tools, schedule information extraction, and interface circuit synthesis, analyzing write and read trace data to optimize data transfer and reduce operation start intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual design method is used for interface circuit, then design flexibility and customization are improved, but design time and labor cost increase significantly
Solution Approach 1:
The design system performs automatic interface circuit design by extracting schedule information from behavioral descriptions and synthesizing interface circuits autonomously, eliminating the need for manual design while maintaining adaptability through configurable parameters in the behavioral description
Solution Approach 2:
The system allows designers to specify interface circuit requirements through parameters in behavioral descriptions (such as data width, timing constraints, and interface protocols), automatically generating customized interface circuits without manual design effort
2Loss of time
If standard interface circuits are used, then design time is reduced, but customization capability and performance optimization are limited
Solution Approach 1:
The system generates customized interface circuits by interpreting parameters specified in behavioral descriptions, allowing full customization of interface characteristics while maintaining automatic design flow and reduced design time
Solution Approach 2:
The interface circuit is synthesized as a separate module based on schedule information extracted from behavioral descriptions of connected circuit modules, allowing independent optimization and customization without affecting the main design flow
3Productivity
If interface circuit operation start interval is reduced, then system throughput is improved, but circuit area and complexity increase
Solution Approach 1:
The system dynamically determines the operation start interval of the interface circuit based on the actual timing requirements extracted from behavioral descriptions, optimizing the balance between throughput and circuit area by avoiding both overly conservative and excessively aggressive timing
4Device complexity
If interface circuit is not optimized, then design simplicity is maintained, but performance bottlenecks occur
Solution Approach 1:
The system automatically optimizes interface circuit performance by extracting schedule information from behavioral descriptions and synthesizing optimized interface circuits without requiring manual intervention, maintaining design simplicity while eliminating performance bottlenecks
Data Source
AI summary
An information processing device includes: a memory; a processor coupled to the memory and configured to: perform, based on input descriptions of a first circuit module that performs a first task and a second circuit module that receive data output from the first circuit module and performs a second task, high-level synthesis of the first circuit module and the second circuit module; synthesize an interface circuit that includes a memory that performs data transfer between the circuit modules based on write information of the data and read information of the data; calculate a minimum operation start interval of the interface circuit based on the write information of the data and the read information of the data; and provide, when the calculated minimum operation start interval is larger than a minimum operation start intervals of the first circuit module and the second circuit module, a storage element in the interface circuit.