Interface Circuitry for Bypassing Home Node in Data Transfer
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Solution Overview
Problem
Current data transfer protocols, such as the CHI protocol, require significant buffering and data traffic due to the need for write data to flow freely through a home node, which can lead to inefficiencies and incompatibilities with other protocols like AXI/ACE, especially in systems where write data must be routed with the same transaction as a write request.
Innovation Solution
A data processing system where at least one data transmission from a master node to a slave node bypasses the home node, allowing the master node to directly issue data transfers while the home node controls coherency, using interface circuitry to convert between different data transfer protocols, thereby reducing buffering needs and data traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write data is routed through the home node according to CHI protocol, then coherency control is maintained, but buffering requirements and data traffic increase significantly
Solution Approach 1:
The patent segments the data transfer path into two types: requests go through the home node for coherency management, while write data bypasses the home node to reduce buffering requirements. This segmentation allows the system to maintain coherency control where needed while eliminating unnecessary buffering overhead for write operations.
Solution Approach 2:
The patent extracts the write data routing function from the home node by allowing write data to bypass the home node and go directly to slave nodes. This extraction reduces the buffering space requirement at the home node while maintaining coherency control through the request path.
2Productivity
If write data channels are made free-flowing through the home node, then data transfer efficiency improves, but device complexity and buffering requirements increase
Solution Approach 1:
The patent segments the data transfer path into two types: requests go through the home node for coherency management, while write data bypasses the home node to reduce buffering requirements. This segmentation allows the system to maintain coherency control where needed while eliminating unnecessary buffering overhead for write operations.
Solution Approach 2:
The patent extracts the write data routing function from the home node by allowing write data to bypass the home node and go directly to slave nodes. This extraction reduces the buffering space requirement at the home node while maintaining coherency control through the request path.
3Reliability
If the system uses CHI protocol with home node for all data transfers, then coherency is maintained, but adaptability to other protocols like AXI/ACE is reduced
Solution Approach 1:
The interface circuitry acts as an intermediary that translates between different protocols (CHI and AXI/ACE). It receives requests in one protocol format and transfers them to slave nodes using the appropriate protocol, enabling the system to maintain coherency control while being adaptable to multiple protocol standards.
Solution Approach 2:
The interface circuitry provides multi-functionality by supporting multiple data transfer protocols (CHI and AXI/ACE). This universal interface allows the system to work with different protocol requirements while maintaining the same coherency control mechanism through the home node.
4Device complexity
If all data transfers go through the home node, then coherency management is simplified, but data traffic and buffering needs increase
Solution Approach 1:
The patent segments the data transfer path into two types: requests go through the home node for coherency management, while write data bypasses the home node to reduce buffering requirements. This segmentation allows the system to maintain coherency control where needed while eliminating unnecessary buffering overhead for write operations.
Solution Approach 2:
The patent extracts the write data routing function from the home node by allowing write data to bypass the home node and go directly to slave nodes. This extraction reduces the buffering space requirement at the home node while maintaining coherency control through the request path.
Data Source
AI summary
A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.