Interface Circuitry Frequency Scaling in Multi-Tenant SoCs
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Solution Overview
Problem
Adjusting the frequency of operation of interface circuitry in SoCs can disrupt processor-executed processes, impacting performance indicators like latency and determinism, and existing methods fail to effectively balance power consumption and performance without disrupting critical operations.
Innovation Solution
Implementing a utilization-based and priority-based control mechanism for the interface circuitry, where the power manager adjusts the frequency based on the utilization levels of multiple processors and the priority of requesting processes to minimize disruptions and optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of operation of interface circuitry is set to a maximum level, then the performance of the system is maintained, but the power consumption increases
Solution Approach 1:
The patent implements dynamic frequency scaling of the interface circuitry based on real-time processor utilization monitoring. The frequency is adjusted from maximum to lower levels when processors are idle or low-utilization, and scaled back up when high-utilization is detected. This dynamic adaptation allows the system to maintain performance during high-demand periods while reducing power consumption during low-demand periods, resolving the contradiction between constant maximum performance and reduced power usage.
Solution Approach 2:
The patent changes the operating frequency parameter of the interface circuitry based on processor utilization thresholds. When utilization is below a threshold, the frequency is reduced; when above the threshold, the frequency is increased. This parameter adjustment enables the system to optimize the balance between performance and power consumption by adapting the frequency to actual workload demands rather than maintaining a fixed maximum level.
2Use of energy by moving object
If the frequency of operation of interface circuitry is adjusted to reduce power consumption, then power consumption is reduced, but the operations of processor-executed processes are disrupted
Solution Approach 1:
The patent employs a feedback mechanism where processor utilization is continuously monitored and fed back to the frequency control logic. The frequency adjustment is triggered only when utilization falls below a predefined threshold and no processes are in critical states. This feedback-based control ensures that frequency changes occur only when safe, preventing disruptions to active processes while still enabling power savings during truly idle periods.
Solution Approach 2:
The patent checks whether processors are in a critical state before allowing frequency reduction. This preliminary assessment prevents frequency changes during critical process execution, thereby avoiding disruptions. The system waits until it is certain that reducing frequency will not impact active processes before initiating the frequency adjustment, thus maintaining reliability while enabling power savings.
3Use of energy by moving object
If frequency scaling is implemented without considering process priority, then power consumption is reduced, but critical processes may be disrupted
Solution Approach 1:
The patent applies different frequency scaling behaviors to different processes based on their priority levels. Critical processes maintain their guaranteed frequency regardless of overall system utilization, while non-critical processes are subject to frequency reduction. This localized quality approach ensures that frequency scaling benefits are applied selectively only where they do not harm critical operations, thus reducing power consumption without disrupting essential processes.
Solution Approach 2:
The patent dynamically adjusts frequency based on process priority and utilization conditions. The control logic evaluates both the current utilization level and the priority status of running processes before determining the appropriate frequency. This dynamic, multi-condition control ensures that critical processes are protected from frequency changes while non-critical processes benefit from frequency scaling, thereby reducing overall power consumption without compromising critical operations.
Data Source
AI summary
Examples described herein relate to circuitry to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on policy parameters; and adjust a frequency of operation of the interface circuitry based on the monitored utilization data and the determined priority levels of the processes. In some examples, adjust the frequency of operation of the interface circuitry is to prioritize frequency of operation requested by a higher priority workload over a frequency of operations requested by a lower priority workload.