Asynchronous Interface Clock Delay Sampling for Low-Latency 3D Links
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Solution Overview
Problem
Conventional 3D semiconductor devices face challenges in reducing circuit area and power consumption when transmitting data through asynchronous interfaces, as they require large FIFO buffers and multiple delay strings, which hinder low-latency applications and increase power consumption.
Innovation Solution
An interface device with a slave circuit that includes a clock generator, sampler, and comparator, which delays the clock signal based on a variable delay value, adjusts the delay to align sampling signals with input data transitions, eliminating the need for multiple delay strings, thereby reducing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple delay strings are used to delay input data for synchronization, then the data transmission can be synchronized with the clock signal, but the circuit area increases and power consumption increases
Solution Approach 1:
The patent extracts the delay function from the data path and relocates it to the clock path. Instead of delaying multiple bits of input data through multiple delay strings, a single delay string delays the clock signal to achieve the same synchronization effect, thereby reducing circuit area
Solution Approach 2:
The delayed clock signal serves multiple sampling points simultaneously. By delaying the clock and generating multiple sampling signals from it, the system achieves synchronization for multiple data bits without requiring separate delay strings for each bit, reducing both area and power consumption
2Reliability
If multiple delay strings are used to delay input data for synchronization, then the data transmission can be synchronized with the clock signal, but power consumption increases due to repeated transition actions
Solution Approach 1:
The patent extracts the delay function from the data path and relocates it to the clock path. Instead of delaying multiple bits of input data through multiple delay strings, a single delay string delays the clock signal to achieve the same synchronization effect, thereby reducing power consumption
Solution Approach 2:
The patent merges the delay function that was previously distributed across multiple delay strings into a single centralized delay string that operates on the clock signal. This consolidation reduces the total number of active circuits and their associated power consumption
3Reliability
If a FIFO buffer is set in the receiver circuit to temporarily store input data, then data transmission synchronization can be achieved, but the delay of data transmission is determined by the depth of the FIFO buffer and cannot meet low-latency application requirements
Solution Approach 1:
The patent removes the FIFO buffer from the receiver circuit and replaces it with a delay string in the clock path. This extraction eliminates the inherent delay associated with FIFO buffer depth while maintaining synchronization through controlled clock delay and multiple sampling signals
Solution Approach 2:
The patent performs preliminary delay adjustment on the clock signal before it reaches the sampling circuits. By pre-delaying the clock and generating appropriately phased sampling signals, the system achieves synchronization without requiring deep FIFO buffers, thus reducing transmission delay
Data Source
AI summary
An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.