Memory Card Interface Clock Recovery Without Handshake Delay
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Solution Overview
Problem
In UHS-II/-III memory card interface standards, the stabilization time of the inner clock frequency after a state change is lengthy, leading to increased latency due to the need for a handshake check, and the low power mode increases power consumption by keeping the PLL circuit operational during dormancy.
Innovation Solution
An interface system that stops the reference clock supply during dormancy and omits the handshake check upon returning to the active state, utilizing a control voltage memory unit to rapidly lock the inner clock frequency, reducing standby power and enabling quick recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PLL circuit is kept operational during dormancy to maintain clock synchronization, then the synchronization reliability is improved, but the power consumption increases
Solution Approach 1:
The patent extracts the clock generation function from the main PLL circuit during dormancy by using a separate, simplified clock generation mechanism that requires minimal power while maintaining basic synchronization capability. The main PLL circuit is powered down or placed in low-power mode, and only essential clock functions are maintained through alternative means.
Solution Approach 2:
The patent performs preliminary clock synchronization actions before entering dormancy mode, storing synchronization state information in memory. When exiting dormancy, the system retrieves this stored state information to rapidly re-establish synchronization without requiring the full PLL circuit to remain operational, thereby reducing power consumption while maintaining reliability.
2Reliability
If the handshake check is performed after state change to ensure synchronization, then the data transfer reliability is improved, but the latency increases
Solution Approach 1:
The patent performs synchronization checks and stores the results in advance before state changes occur. The synchronization state information is cached in memory, allowing the system to determine whether a handshake check is actually needed after exiting dormancy. This preliminary preparation eliminates unnecessary handshake delays while maintaining reliability when synchronization is already valid.
Solution Approach 2:
The patent uses a simplified, fast synchronization verification mechanism that can quickly determine if full handshake is needed. This lightweight check serves as a preliminary filter, disposing of the need for time-consuming full handshake procedures when synchronization is already established, thereby reducing latency while preserving data transfer reliability.
3Speed
If the inner clock frequency is rapidly locked using control voltage memory unit, then the recovery speed is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent copies the control voltage value from a previously stable operating state and stores it in a memory unit. Upon exiting dormancy, this copied control voltage is rapidly reapplied to the PLL circuit, forcing it to lock onto the correct frequency much faster than conventional startup. This copying approach achieves rapid recovery without requiring complex control logic or multiple iterative adjustment mechanisms.
Solution Approach 2:
The patent performs the action of capturing and storing the optimal control voltage value in advance, before dormancy begins. This preliminary storage of the correct control parameter eliminates the need for time-consuming voltage adjustment sequences during recovery, achieving fast lock-on while using simple memory storage rather than complex real-time control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes standby power consumption and reduces the time required for synchronization, allowing immediate data transfer after a state change without the need for a handshake check, thus enhancing the interface system's efficiency and recovery speed.
Implementation Method 1
The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data.
Data Source
AI summary
According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.