Interface Control Circuit for I2C SPI Signal Conversion

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Solution Overview

Problem

Conventional integrated circuits with both I2C and SPI interfaces face limitations due to the lower operation speed of I2C compared to SPI, and the complexity of implementing a combo design in a single chip, which complicates signal conversion and access control for non-volatile memory.

Innovation Solution

An interface control circuit comprising an interface wrapper, logic circuit, multiplexer, and command decoder that converts signals between I2C and SPI formats, generating appropriate command signals to enable access control for non-volatile memory, allowing for a combo interface solution that supports multiple signal formats.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If I2C interface is used, then hardware structure is simpler, but operation speed is lower

Engineering Contradiction:
Improvehardware structureVSAvoidoperation speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The interface control circuit is designed to support both I2C and SPI interfaces within a single chip, allowing the same hardware to perform multiple interface functions. This enables the system to leverage the simple hardware structure of I2C while also accessing the higher speed capabilities of SPI when needed, resolving the contradiction between structural simplicity and operational speed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If SPI interface is used, then operation speed is higher, but hardware structure is more complex

Engineering Contradiction:
Improveoperation speedVSAvoidhardware structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent combines both I2C and SPI interface circuits within a single chip, merging their functionalities into one integrated solution. This allows the system to access the high-speed capabilities of SPI while sharing common hardware resources with I2C, thereby reducing overall hardware complexity compared to implementing separate dedicated circuits for each interface type.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If I2C and SPI combo design is implemented in a single chip, then cost of product mask is saved, but signal conversion and access control becomes more complex

Engineering Contradiction:
Improvecost of product maskVSAvoidsignal conversion and access control
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The interface control circuit acts as an intermediary between the external interface signals and the internal memory access logic. It receives signals from either I2C or SPI interface, performs the necessary format conversion and command decoding, and generates the appropriate internal control signals. This intermediary layer simplifies the overall design by centralizing the conversion logic within a dedicated control circuit, making the system easier to manufacture while managing the complexity of signal conversion.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11144491B1Integrated circuit and interface control circuit thereof
Publication Date: 2021.10.12 WINBOND ELECTRONICS CORP
  • US11144491B1 patent drawing
  • US11144491B1 patent drawing
  • US11144491B1 patent drawing

AI summary

An interface control circuit includes an interface wrapper, a logic circuit, a multiplexer and a command decoder. The interface wrapper transceives a plurality of first signals in a first interface, converts the first signals to a plurality of second signals in a second interface, and generates at least one first command signal according to the first signals. The logic circuit receives the second signals, and generates a second command signal according to the second signals. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal and generates the decoded command according to the third command signal.