Hierarchical Interface Decomposition for FPGA Timing Compliance
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Solution Overview
Problem
Automated place-and-route electronic design automation (EDA) solutions often fail to meet the strict timing requirements of interface portions in circuit designs, particularly in FPGA implementations, leading to routing congestion and delays that exceed the required timing specifications.
Innovation Solution
The method involves decomposing the interface portion of a circuit design into multiple levels, where each level specifies connections between a first set of circuit elements with fixed locations and a second set of circuit elements, allowing for level-by-level placing-and-routing, with the main portion routed after the interface elements are placed-and-routed, optimizing timing by determining actual timing based on placement and routing in each level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated place-and-route EDA solutions are used, then productivity is improved, but timing requirements cannot be met
Solution Approach 1:
The interface portion is divided into multiple levels, where each level contains a subset of circuit elements and connections. This segmentation allows the automated EDA tool to process and optimize timing for each level independently, improving overall timing compliance while maintaining automation benefits.
Solution Approach 2:
The method performs preliminary placement and routing of circuit elements in each level before moving to the next level. This preliminary action ensures that timing-critical paths are established early, allowing subsequent levels to be optimized based on the timing constraints imposed by previous levels.
2Ease of operation
If traditional place-and-route methods are used, then ease of operation is maintained, but routing congestion occurs
Solution Approach 1:
By segmenting the interface portion into multiple levels, the method reduces the complexity of routing decisions at any single level. This segmentation prevents routing congestion by distributing connections across multiple levels, where each level handles a manageable subset of connections.
Solution Approach 2:
The method introduces a hierarchical dimension to the traditional planar routing approach. By organizing circuit elements and connections into multiple levels, the routing problem is transformed from a two-dimensional congestion issue to a multi-dimensional optimization problem, allowing routes to be established in a hierarchical manner that avoids congestion.
3Device complexity
If traditional place-and-route methods are used, then device complexity is reduced, but timing optimization is insufficient
Solution Approach 1:
The interface portion is segmented into multiple levels, each with specific timing optimization requirements. This segmentation allows targeted timing optimization at each level without requiring complete redesign of the entire interface portion, thus improving timing precision while controlling overall complexity.
Solution Approach 2:
Different levels of the interface portion are optimized with different levels of detail and complexity. Levels closer to the fixed locations receive more intensive optimization, while subsequent levels use progressively simpler optimization strategies, achieving local quality optimization that balances complexity and timing precision.
Data Source
AI summary
A netlist of a circuit design includes an interface portion and a main portion. The interface portion is decomposed into multiple levels. Each level specifies connections between a respective first set of circuit elements and a respective second set of circuit elements. The second set of circuit elements in each level, except a last level, includes the first set of circuit elements in a next level. The first set of circuit elements identified in a first level of the multiple levels have fixed locations. The second set of circuit elements in the multiple levels is placed-and-routed. The placing-and-routing of the second set of circuit elements in one level is completed before commencing placing-and-routing of the second set of circuit elements in the next level. The main portion is placed-and-routed after placing-and-routing the second set of circuit elements in the multiple levels.