Interface Device Parallel Data Reception via Segmented Buffer
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Solution Overview
Problem
Existing interface devices with a single reception buffer cause undesired delays and latencies because data reception by one interface circuit must be completed before another can start, limiting parallel data reception capabilities.
Innovation Solution
Implementing a plurality of interface circuits that share a single reception buffer, where each interface circuit acquires and identifies packets with a unique tag ID, allowing parallel data reception and storage in the buffer, enabling the processor to manage and process packets efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reception buffer is used for multiple interface circuits, then device complexity is reduced, but data reception speed and parallel processing capability deteriorate
Solution Approach 1:
The reception buffer is segmented into multiple buffer regions, each assigned to a specific interface circuit. This segmentation allows multiple interface circuits to write data to different buffer regions simultaneously without conflict, while still using a single physical buffer memory, thus maintaining low device complexity while improving data reception speed and parallel processing capability.
2Ease of manufacture
If a single reception buffer is shared by multiple interface circuits, then manufacturing cost is reduced, but productivity and data processing throughput deteriorate
Solution Approach 1:
The buffer is divided into multiple buffer regions with each region dedicated to a specific interface circuit. This allows parallel data reception from multiple interfaces simultaneously, significantly improving data processing throughput while still using a single shared buffer memory, thus maintaining ease of manufacture and low cost.
Solution Approach 2:
A buffer management unit acts as an intermediary between multiple interface circuits and the buffer regions. It manages the allocation and coordination of buffer regions to different interface circuits, enabling efficient parallel data reception and processing while maintaining simple buffer implementation.
3Productivity
If multiple buffer regions are created in a shared buffer, then parallel data reception capability is improved, but device complexity increases
Solution Approach 1:
The buffer is segmented into multiple buffer regions that can be independently accessed by different interface circuits. This segmentation enables parallel data reception while keeping the buffer management structure relatively simple through dedicated region assignment rather than complex dynamic allocation.
Solution Approach 2:
The single buffer memory serves multiple functions by being divided into multiple buffer regions that can handle different interface circuits simultaneously. This multi-functionality approach improves parallel data reception capability while avoiding the need for multiple separate buffer memories, thus limiting the increase in device complexity.
Data Source
AI summary
In accordance with an embodiment, an interface device comprises a plurality of interface circuits which respectively corresponds to different transmission paths and sequentially acquires a plurality of packets formed by dividing data which is an object of any one of plural types of information processing via the corresponding transmission paths, a reception buffer and a processor. The processor writes the packet acquired by each of the plurality of the interface circuits in the reception buffer in association with an identification code for identifying the interface circuit acquiring the packet, sequentially reads a plurality of packets associated with the same identification code among the packets stored in the reception buffer from the reception buffer, and delivers the read packets to the information processing on the data which is a basis of the packet.