Interface Die for Stacked Silicon Interconnect HBM Integration

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Solution Overview

Problem

Existing integrated circuit packaging technologies face challenges in efficiently adding high bandwidth memory (HBM) capabilities to programmable ICs like FPGAs without disrupting the existing logic circuit architecture, requiring complex requalification and additional circuitry that alters the clocking network and removes logic blocks.

Innovation Solution

The integration of an interface die and HBM buffer die, sharing the same wafer-level substrate but separated by a scribe line, uses interposer interconnections to connect the programmable IC die to the HBM die, allowing for high-bandwidth connections without altering the programmable IC architecture, and using the same mask set as if they were a single die.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If HBM capabilities are added to programmable ICs using existing packaging technologies, then memory bandwidth is improved, but device complexity and qualification requirements increase

Engineering Contradiction:
Improvememory bandwidthVSAvoidpackaging complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The system is segmented into distinct functional components: a programmable IC die, a fixed feature die (HBM buffer), and an interposer with integrated interconnection lines. This segmentation allows each component to be optimized independently while maintaining high bandwidth through the interposer's dedicated interconnect structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An interposer is introduced as an intermediary component between the programmable IC die and the fixed feature die. The interposer contains interconnection lines that facilitate high-speed data transfer, effectively mediating the connection and enabling HBM capabilities without directly modifying the programmable IC architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If HBM capabilities are added to programmable ICs by integrating additional circuitry, then memory bandwidth is improved, but qualification time and costs increase

Engineering Contradiction:
Improvememory bandwidthVSAvoidqualification time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

By separating the HBM buffer functionality into a distinct fixed feature die rather than integrating it into the programmable IC die, the system avoids the need to requalify the entire programmable IC. Only the fixed feature die requires qualification for HBM operations, significantly reducing qualification time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interposer serves as a mediator that enables HBM functionality through external connection rather than internal integration. This approach allows the programmable IC to maintain its original qualified status while the fixed feature die provides the additional HBM capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If the programmable IC architecture is modified to add HBM support, then memory bandwidth is improved, but adaptability of existing designs decreases

Engineering Contradiction:
Improvememory bandwidthVSAvoiddesign flexibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The HBM buffer functionality is extracted from the programmable IC die and implemented as a separate fixed feature die. This extraction preserves the original programmable IC architecture and its design flexibility while adding HBM capabilities through the external fixed feature die connected via the interposer.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10784121B2Standalone interface for stacked silicon interconnect (SSI) technology integration
Publication Date: 2020.09.22 XILINX INC
  • US10784121B2 patent drawing
  • US10784121B2 patent drawing
  • US10784121B2 patent drawing

AI summary

Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.