Interface Die for Stacked Silicon Interconnect HBM Integration
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Solution Overview
Problem
Existing integrated circuit packaging technologies face challenges in efficiently integrating high bandwidth memory (HBM) with programmable ICs like FPGAs without disrupting the existing architecture, as adding necessary connections would require significant changes and requalification of the IC die, which is complex and costly.
Innovation Solution
The introduction of an interface die compatible with both the programmable IC and HBM, using interposer interconnections to connect the HBM buffer die to the FPGA, allowing for high-bandwidth connections without altering the programmable IC die, and using a shared wafer-level substrate with a scribe line to separate the dies, enabling seamless integration of HBM into existing SSI technology without requalifying the FPGA.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If HBM connections are added to programmable IC die, then high bandwidth memory capability is improved, but device complexity and requalification requirements worsen
Solution Approach 1:
An interface die is introduced as an intermediary component between the programmable IC die and the HBM buffer die. This interface die contains the necessary interconnection logic and protocols to enable HBM functionality without modifying the existing programmable IC die architecture. The interface die acts as a mediator that translates and manages data flow between the two different technologies, thereby adding HBM capability while preserving the original IC design.
Solution Approach 2:
The system is segmented into separate functional components: the programmable IC die, the interface die, and the HBM buffer die. Each component maintains its own architecture and optimization, allowing independent design and manufacturing. The HBM buffer die is stacked above the interface die, creating a modular stacked configuration that enables HBM functionality without disrupting the programmable IC die below.
2Reliability
If interconnection lines are routed through interposer, then electrical connection between dies is improved, but manufacturing complexity worsens
Solution Approach 1:
The interconnection architecture transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. Multiple interconnection lines are routed through the interposer in the vertical dimension, allowing dense electrical connections between the programmable IC die, interface die, and HBM buffer die without increasing the lateral footprint. This dimensional transition enables complex interconnect patterns while maintaining manufacturability through established 3D stacking processes.
Data Source
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Figure 3A~3B
AI summary
Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package (200) generally includes a package substrate (202); at least one interposer (204) disposed above the package substrate (202) and comprising a plurality of interconnection lines (310, 312); a programmable IC die (302) disposed above the interposer (204); a fixed feature die (304) disposed above the interposer (204); and an interface die (306) disposed above the interposer (204) and configured to couple the programmable IC die (302) to the fixed feature die (304) using a first set of interconnection lines (310) routed through the interposer (204) between the programmable IC die (302) and the interface die (306) and a second set of interconnection lines (312) routed through the interposer (204) between the interface die (306) and the fixed feature die (304).