Interface Die Test Circuit for HBM Channel Noise Evaluation
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Solution Overview
Problem
High Bandwidth Memory (HBM) devices face limitations in testing multiple channels simultaneously due to space constraints and interference between channels, which hinders effective noise interference testing and chip validation.
Innovation Solution
The implementation of a test input/output circuit and Built-In Self Test (BIST) circuit with a serial bus selector and test channel selectors allows for independent testing of multiple channels by controlling test enable signals, enabling simultaneous testing and noise interference evaluation between channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple channels are tested simultaneously using existing test methods, then testing efficiency is improved, but channel interference and test accuracy deteriorate due to noise between channels
Solution Approach 1:
The patent divides the test system into separate test pads for each channel (CH0-CH3), allowing independent testing of each channel while maintaining the capability to test multiple channels simultaneously. The segmentation is achieved by providing dedicated test pads and control logic for each channel, which prevents noise interference while improving testing efficiency.
Solution Approach 2:
The patent introduces a test pad as an intermediary component between the external tester and the memory channels. This test pad enables controlled signal injection and isolation, allowing multiple channels to be tested simultaneously without direct interference. The test pad acts as a mediator that manages signal routing and prevents cross-channel noise.
2Adaptability or versatility
If the area of test pad is increased to accommodate multiple channels, then multiple channel testing is enabled, but chip footprint increases
Solution Approach 1:
The patent combines multiple test functions into a single integrated test pad structure. Instead of providing separate large test areas for each channel, the design merges the test functionality for multiple channels into shared test pad infrastructure with selective activation, reducing the overall footprint while maintaining multi-channel testing capability.
Solution Approach 2:
The test pad is designed with multi-functionality to serve multiple channels. A single test pad can be configured to test different channels through control signals, making the test pad structure universal rather than dedicated to a single channel. This universality reduces the total area required compared to having separate dedicated test pads for each channel.
3Reliability
If APG occupies large area on I/F die, then comprehensive testing is possible, but footprint constraints prevent including multiple APGs
Solution Approach 1:
Instead of implementing multiple full APG circuits, the patent uses a single APG that generates test patterns and distributes them to multiple channels through the test pad infrastructure. The test patterns are effectively copied and distributed to different channels without requiring multiple independent APG instances, thus maintaining comprehensive testing capability while reducing footprint.
Solution Approach 2:
The patent transitions from a spatial arrangement where each channel would require its own APG instance to a temporal/distributive arrangement where a single APG serves multiple channels through time-multiplexed or distributed pattern generation. This dimensional change in the testing architecture allows comprehensive multi-channel testing without proportionally increasing the die area.
Data Source
AI summary
Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.