Interface FPGA Routing for Emulator Reconfiguration Isolation
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Solution Overview
Problem
In emulation environments with multiple intellectual property units, reconfiguring hundreds of field programmable gate arrays (FPGAs) is time-consuming and inefficient due to the need to reconfigure all FPGAs when changes are made to any unit, as signals between units often require routing through other emulated units.
Innovation Solution
Configuring an emulator to route connections between intellectual property units through interface FPGAs that do not emulate any units, allowing only the FPGAs of the modified unit and its interface FPGAs to be reconfigured, thereby isolating the FPGAs of other units from reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signals between IP units are routed through FPGAs of other IP units, then connections between units can be established, but all FPGAs must be reconfigured when any unit changes, increasing reconfiguration time
Solution Approach 1:
The patent segments the FPGA system into two distinct groups: emulated unit FPGAs that execute IP unit functions, and interface FPGAs that handle inter-unit signal routing. This segmentation allows independent reconfiguration of emulated unit FPGAs without affecting other units, as interface FPGAs serve as isolated routing intermediaries. The segmentation resolves the contradiction by enabling routing flexibility through interface FPGAs while preventing cascaded reconfiguration of all FPGAs.
Solution Approach 2:
Interface FPGAs act as intermediary components between emulated unit FPGAs, handling signal routing without requiring the emulated units themselves to be reconfigured. When an IP unit changes, only its corresponding emulated unit FPGA and the interface FPGAs it connects to need reconfiguration, not all FPGAs in the system. This intermediary approach maintains routing flexibility while minimizing reconfiguration scope.
2Reliability
If all FPGAs are reconfigured when an IP unit changes, then the emulation remains accurate, but debugging becomes inefficient due to unnecessary reconfiguration of unchanged units
Solution Approach 1:
The patent divides the FPGA system into emulated unit FPGAs and interface FPGAs, enabling selective reconfiguration. When debugging an IP unit, only the corresponding emulated unit FPGA and its connected interface FPGAs are reconfigured, while other emulated unit FPGAs remain unchanged. This segmentation maintains emulation accuracy for the modified unit while avoiding unnecessary reconfiguration of other units, thereby improving debugging efficiency.
Solution Approach 2:
Instead of reconfiguring all FPGAs (excessive action), the patent implements partial reconfiguration affecting only the necessary emulated unit FPGA and its connected interface FPGAs. This partial action approach maintains sufficient emulation accuracy for the modified IP unit while significantly reducing reconfiguration overhead and improving debugging productivity.
3Loss of time
If interface FPGAs are used to route connections, then only modified unit FPGAs and their interface FPGAs need reconfiguration, but the system complexity increases
Solution Approach 1:
Interface FPGAs perform multiple functions: routing signals between different emulated unit FPGAs and providing isolation between units. This multi-functionality justifies the added structural complexity by enabling fast reconfiguration and reducing the reconfiguration scope when IP units change. The interface FPGAs serve as universal routing nodes that benefit the entire emulation system.
Solution Approach 2:
The patent introduces interface FPGAs as separate routing nodes between emulated unit FPGAs. This segmentation increases structural complexity but enables independent reconfiguration of emulated units without cascading effects. The interface FPGAs act as fixed routing infrastructure that isolates reconfiguration to minimal scopes, reducing reconfiguration time despite the added structural layer.
Data Source
AI summary
A host system receives a description of a design under test (DUT) that includes multiple IP units and is to be emulated by an emulator. The host system compiles the description of the DUT, which includes synthesizing the description, partitioning the DUT, and mapping the partitions to FPGAs included in the emulator that will emulate the DUT. Each IP unit is part of a single partition or partitioned into multiple partitions and mapped to a different set of FPGAs. The host system identifies connections in the DUT between IP units. The host system designates one or more FPGAs of the emulator that have not been allocated to emulate IP units as interface FPGAs. The host system determines a route for each of the identified connections through one of the interface FPGAs. The connections are routed so that there are no direct connections between the sets of FPGAs of two IP units.