Interface-Free Metal Gate Stack Fabrication
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Solution Overview
Problem
Conventional fabrication techniques for high-k dielectric and metal gate transistors result in defects such as charged oxygen vacancies, leading to shifts in threshold voltage (Vt), especially in p-type devices, due to extrinsic oxygen entering the high-k gate layer during processing.
Innovation Solution
A method involving the formation of a high dielectric constant layer, a metal layer, and a silicon-containing layer, with a disposable spacer and selective removal of silicon dioxide to create an interface-free gate stack, followed by re-oxidation to introduce oxygen and reduce charged defects, ensuring a surface free of oxidized layers on the metal gate conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication techniques are used for MHK transistors, then metal contacts can be formed, but charged oxygen vacancies are created that alter the threshold voltage
Solution Approach 1:
The patent applies preliminary action by forming the silicon-containing layer over the metal layer before subsequent processing steps. This pre-formed layer acts as a protective barrier that prevents oxygen ingress during high-temperature processing, thereby preventing charged oxygen vacancy formation while still allowing metal contact formation to occur.
Solution Approach 2:
The silicon-containing layer serves as an intermediary protective layer between the metal contact and the external environment. This intermediate layer blocks oxygen diffusion paths without interfering with the electrical function of the metal contact, resolving the contradiction between ease of manufacture and threshold voltage stability.
2Ease of manufacture
If extrinsic oxygen enters the high-k gate layer during processing, then the high-k layer can be formed, but the electrical properties of the MHK transistor are altered
Solution Approach 1:
The silicon-containing layer is formed preliminarily over the metal layer before subsequent high-temperature processing steps. This pre-formed protective layer prevents oxygen from entering the high-k gate layer during processing, thereby maintaining electrical property stability while still allowing the high-k gate layer to be formed.
Solution Approach 2:
The silicon-containing layer acts as an intermediary barrier that blocks oxygen diffusion to the high-k gate layer. This intermediate protective layer allows the high-k gate layer formation process to proceed while preventing oxygen contamination that would alter electrical properties.
3Reliability
If high-temperature processing is used to remove oxygen defects, then oxygen vacancies can be reduced, but the threshold voltage shifts are more acute for p-type devices
Solution Approach 1:
The silicon-containing layer is formed in advance to create a protective barrier before any high-temperature processing. This preliminary protective layer prevents oxygen ingress during thermal processing, allowing oxygen vacancy reduction through controlled means while preventing threshold voltage shifts, especially in p-type devices.
Solution Approach 2:
The silicon-containing layer serves as an intermediary protective barrier during thermal processing. It allows controlled oxygen vacancy reduction while blocking uncontrolled oxygen ingress that would cause threshold voltage shifts, thereby maintaining manufacturing precision even when reliability improvements are sought.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the threshold voltage by enhancing oxygen flow and reducing the need for high-temperature processing, resulting in improved electrical properties and closer Fermi level alignment to the valence band edge, optimizing device performance.
Implementation Method 1
A silicon dioxide layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer
Implementation Method 2
forming a high dielectric constant layer on a semiconductor layer
Data Source
AI summary
A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.