Interface Mapping Unit for Virtual Accelerator Dispatch

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Solution Overview

Problem

In data processing systems where an accelerator acts as a shared resource for multiple applications, existing methods for dispatching tasks to the accelerator often require going through the operating system and hypervisor, leading to increased latency and inefficiency, especially in virtualized systems with multiple virtual machines.

Innovation Solution

The implementation of an interface mapping unit that dynamically maps virtual accelerator input/output interfaces to physical register input/output interfaces, allowing applications to directly access and dispatch tasks to the accelerator without needing to go through the operating system and hypervisor, thereby reducing latency and supporting a large number of virtual machines with a limited number of physical interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If applications access the accelerator through the operating system and hypervisor using physical register interfaces, then the system maintains proper virtualization control and resource management, but the task dispatch latency increases and efficiency decreases

Engineering Contradiction:
Improvevirtualization controlVSAvoidtask dispatch latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces a virtualization interface as an intermediary layer between applications and physical register interfaces. This interface includes virtual register interfaces that applications can access directly, while the virtualization interface translates these to physical register interfaces only when necessary. This mediator approach reduces latency by allowing direct access while maintaining virtualization control through the translation layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the interface architecture into multiple layers: physical register interfaces for direct hardware access, virtual register interfaces for application-level access, and a virtualization interface that manages the mapping between them. This segmentation allows applications to interact with simplified virtual interfaces while the complex physical interface management is handled separately by the virtualization layer.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple virtual machines share a limited number of physical accelerator interfaces, then resource utilization is improved, but the ability to support a large number of virtual machines is constrained

Engineering Contradiction:
Improveresource utilizationVSAvoidnumber of supported virtual machines
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements virtual register interfaces that can be universally accessed by multiple virtual machines. These virtual interfaces act as multi-functional proxies that can represent any physical register interface, allowing any virtual machine to access any accelerator resource through the virtualization interface. This universality enables a large number of virtual machines to share a limited number of physical interfaces without constraint.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent creates virtual copies of physical register interfaces. Instead of providing direct access to physical interfaces, the system creates virtual representations (copies) of these interfaces that applications can access. The virtualization interface then manages the mapping between these virtual copies and the actual physical interfaces, allowing multiple virtual machines to simultaneously access the same physical resources through their respective virtual copies.

Inventive Principle:
Principle #26Copying

3Productivity

If direct access to physical register interfaces is provided to applications, then task dispatch efficiency is improved, but system complexity and security control become problematic

Engineering Contradiction:
Improvetask dispatch efficiencyVSAvoidinterface management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The virtualization interface serves as a mediator that handles the complexity of interface management. Applications interact with simplified virtual register interfaces, while the virtualization interface manages the complex mapping, translation, and access control to physical register interfaces. This intermediary approach provides direct access efficiency to applications while centralizing the complexity management in the virtualization layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The virtual register interfaces are designed to be self-service for applications, providing a simplified, consistent interface that applications can use without needing to understand the underlying physical interface complexity. The virtualization interface automatically handles the translation and mapping operations, making the complex physical interface management transparent to applications and thereby reducing perceived complexity while maintaining efficiency.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10261813B2Data processing system for dispatching tasks from a plurality of applications to a shared resource provided by an accelerator
Publication Date: 2019.04.16 ARM LTD
  • US10261813B2 patent drawing
  • US10261813B2 patent drawing
  • US10261813B2 patent drawing

AI summary

A data processing system comprising an accelerator that acts as a common shared resource for plural applications executing in respective virtual machines. The data processing system includes an interface mapping unit that facilitates the submission of tasks from applications to the accelerator. The interface mapping unit includes physical registers that act as physical register input/output interfaces for the accelerator. The interface mapping unit exposes a plurality of virtual accelerator input/output interfaces to the applications that are then dynamically mapped to the physical register input/output interfaces by the interface mapping unit to allow applications to access, and thereby submit a task to, a given physical register input/output interface.