Interface Circuit Port Mapping to Eliminate PCB Crossover Routing

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Solution Overview

Problem

The complexity and cost of circuit board fabrication and packaging increase due to the need for multiple chip connections with different pin arrangements, leading to crossover connections among chip pins.

Innovation Solution

An interface circuit with an I/O processing sub-circuit, path selection sub-circuit, and I/O ports, where the path selection sub-circuit customizes the signal output and input paths to match the external device's port arrangement, allowing for non-crossing connections using a single or reduced number of circuit layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple chips are connected on the same circuit board to achieve circuit functions, then circuit functionality is improved, but the number of copper layers increases leading to increased manufacturing complexity and cost

Engineering Contradiction:
Improvecircuit functionalityVSAvoidcircuit board manufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple separate chips into a single integrated chip. The interface circuit integrates multiple I/O ports with different pin arrangements within one chip, eliminating the need for multiple separate chips and their corresponding copper layers on the circuit board.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interface circuit provides multi-functionality by incorporating multiple I/O ports that can accommodate different pin arrangements (first pin arrangement and second pin arrangement) within a single chip. This universal design allows the same chip to interface with multiple types of external devices with different pin configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple chips with different pin arrangements are used, then circuit adaptability is improved, but crossover connections among chip pins increase requiring more copper layers

Engineering Contradiction:
Improvepin arrangement compatibilityVSAvoidnumber of copper layers
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Multiple I/O ports with different pin arrangements are merged into a single integrated circuit chip, reducing the need for multiple separate chips and their associated copper layers on the circuit board.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent resolves the pin arrangement mismatch by changing the dimension of integration from the circuit board level to the chip level. By integrating multiple pin arrangements within one chip, the need for multiple copper layers on the board is eliminated.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If chip pin arrangements are customized for different functions, then circuit performance is improved, but the complexity of circuit board fabrication increases

Engineering Contradiction:
Improvecircuit performanceVSAvoidcircuit board fabrication ease
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges multiple customized pin arrangements into a single integrated chip, allowing each I/O port to be optimized for its specific function while simplifying the overall circuit board fabrication process.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11140777B2Interface circuit, chip containing interface circuit and manufacturing method thereof
Publication Date: 2021.10.05 SHENZHEN SANDIYIXIN ELECTRONICS CO LTD
  • US11140777B2 patent drawing
  • US11140777B2 patent drawing
  • US11140777B2 patent drawing

AI summary

Disclosed is an interface circuit, a chip containing an interface circuit and a manufacturing method thereof. The interface circuit includes an I/O processing sub-circuit, a path selection sub-circuit, and at least two I/O ports. The I/O processing sub-circuit, the path selection sub-circuit, and the at least two I/O ports are electrically connected in sequence. The path selected by the path selection sub-circuit can enable a first and a second electrical signal to be transmitted through the I/O ports that are configured to correspond to the ports of the external device through which the first and second electrical signals are transmitted. That is, the path selection sub-circuit can customize the layout of the signal-input/output I/O ports of the interface circuit according to the layout of the ports of the external device.