Parameterized Interface Protection for SoC Communication Verification
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Solution Overview
Problem
The challenge in verifying communication compatibility between components in integrated circuits and external IP blocks, particularly in SoCs, leads to increased design time and potential engineering errors, while existing software and firmware verification methods incur high processor loading and lag times.
Innovation Solution
A system and method that adds hardware validation at component interfaces by modifying electronic designs, using interface protection parameters to create a model for verification logic, which includes generators and checkers to ensure functional communication, and can auto-correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If communication verification is performed in software or firmware, then the system can check component functionality, but processor loading increases and response time increases due to execution lag
Solution Approach 1:
The patent replaces software/firmware-based verification (which uses processor cycles) with hardware-based verification using dedicated verification circuits and logic that operate independently of the main processor, thereby eliminating processor loading while maintaining verification capability
Solution Approach 2:
The patent introduces intermediary hardware components (verification logic, checkers, and monitoring circuits) that mediate between communicating components and the processor, enabling verification to occur in parallel without blocking processor operations
2Reliability
If communication verification is performed in software or firmware, then the system can check component functionality, but lag time increases between error occurrence and error detection
Solution Approach 1:
The patent implements continuous hardware-based monitoring of communication interfaces that operates simultaneously with data transmission, enabling real-time error detection without the periodic sampling or interrupt-driven delays inherent in software-based verification
Solution Approach 2:
The patent replaces software-based error detection (which suffers from execution lag) with hardware-based detection circuits that provide immediate error signaling at the interface level, reducing error detection time to near-instantaneous
3Adaptability or versatility
If manual communication verification components are written by IC designers, then custom verification can be created, but design time increases and engineering errors increase
Solution Approach 1:
The patent uses template-based verification component generation that replicates proven verification patterns and logic structures, allowing rapid creation of verified verification code without manual writing, thereby reducing design time while maintaining adaptability through parameter customization
Solution Approach 2:
The patent creates universal verification templates and IP blocks that can be applied across multiple interface types and communication protocols, enabling a single set of verified components to serve multiple purposes and reducing overall design time while maintaining customizability
4Adaptability or versatility
If manual communication verification components are written by IC designers, then custom verification can be created, but the potential for engineering errors increases
Solution Approach 1:
The patent employs pre-verified template code and standardized verification patterns that have been thoroughly tested and validated, eliminating manual coding errors while maintaining the ability to adapt to different interfaces through parameter configuration rather than code modification
Solution Approach 2:
The patent implements self-verifying verification components that include built-in consistency checks and validation logic to detect and prevent engineering errors during the verification setup process, thereby automatically ensuring correctness without requiring extensive manual review
Data Source
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AI summary
A system and method for adding interface protection (408b, 412b, 414b, 416b) to an electronic design (402b) using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.