Interface System Dynamic Mode Transition for Bandwidth
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Solution Overview
Problem
Conventional electronic interfaces, such as JTAG, operate at limited bandwidth, making them inadequate for current or new uses, and lack compatibility with existing configurations, necessitating a higher speed interface while maintaining backward compatibility.
Innovation Solution
An interface system that dynamically transitions between a standard mode and a high-speed mode using low-voltage differential signaling, enabling communication at up to 300 MHz, while ensuring backward compatibility through a mode controller and dual transport protocol circuitry, allowing for seamless switching between modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional JTAG interface is used, then backward compatibility is maintained, but bandwidth is limited to about 25 MHz
Solution Approach 1:
The interface system dynamically switches between standard JTAG mode and high-speed LVDS mode based on operational requirements. The mode controller enables the system to transition from the conventional 25 MHz JTAG interface to a high-speed differential signaling interface operating at up to 300 MHz, providing adaptive bandwidth adjustment while maintaining protocol compatibility through a unified physical layer that supports both modes
Solution Approach 2:
The physical interface is designed with multi-functionality to support both standard JTAG protocol and high-speed LVDS protocol using the same physical pins and connector. The dual transport protocol circuitry allows a single interface to serve multiple purposes: legacy JTAG operations for compatibility and high-speed differential signaling for enhanced bandwidth, eliminating the need for separate interface hardware
2Productivity
If high speed interface is implemented, then bandwidth is improved to up to 300 MHz, but device complexity increases due to dual transport protocol circuitry
Solution Approach 1:
The patent merges the standard JTAG transport protocol circuitry and high-speed LVDS transport protocol circuitry into a unified interface system. Both protocol implementations share common components including the physical interface pins, mode controller, and data path, reducing the overall complexity compared to having completely separate interfaces. The mode controller coordinates both protocol circuits to operate correctly in their respective modes
Solution Approach 2:
The mode controller acts as an intermediary that manages the complexity of switching between protocols. It monitors operational mode requirements and coordinates the activation of appropriate transport protocol circuitry, shielding the user from the underlying complexity of having dual protocol support while enabling high-speed operation when needed
3Adaptability or versatility
If dynamic mode switching is enabled, then adaptability is improved, but reliability may be affected during transition periods
Solution Approach 1:
The mode controller performs preliminary actions during mode transitions by first disabling the current transport protocol circuitry before activating the new one. This sequential disabling/enabling approach ensures that only one protocol circuitry is active at a time, preventing communication instability during transitions. The system prepares the new mode configuration before switching to ensure smooth and reliable operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interface system achieves significantly higher bandwidth performance while maintaining compatibility with existing protocols, enabling efficient communication and recovery from external disturbances by dynamically switching between standard and high-speed modes.
Implementation Method 1
The second type physical interface is configured for low-voltage differential signaling at a second, higher bandwidth
Data Source
Figure 1
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Figure 4
AI summary
An interface including first (126) and second (128) transport protocol circuitry, a memory (302) and a mode controller (124). The interface includes first (401) and second (411) physical interface types which are both selectively enabled to interface a set of pads (202). The first transport protocol circuitry is operative with the first type physical interface in a first mode (702 STD) and the second transport protocol circuitry is operative with the second type physical interface in a second mode (708 HS). The memory stores a mode value (MODE_HS) indicative of the operating mode. The mode controller enables one of the physical interface types and a corresponding transport protocol based on the mode value. The first mode is the default mode, and the mode controller enables dynamic transition to the second mode. An escape indication (ESC) may be enabled during the second mode for dynamic transition back to the first mode. Programmable timing values (TIMER 1, TIMER 2) may be used to facilitate mode transitions.