Programmable Interface Unit for Parallel Data Transfer
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Solution Overview
Problem
Conventional interface units are unable to efficiently manage both task-synchronous and continuous data transfer in real-time systems, leading to latency and jitter issues when handling high-frequency sensor signals, as they require synchronized cycle rates for data processing.
Innovation Solution
A programmable interface unit with two categories of software routines, one for task-synchronous and one for continuous data transfer, allowing different cycle rates for each category, enabling parallel data transfer without compromising latency or jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interface processors are configured for task-synchronous data transfer with synchronized cycle rates, then data processing is coordinated with task execution, but high-frequency sensor signals suffer from subsampling and increased latency
Solution Approach 1:
The interface unit is divided into multiple interface processors, each capable of independent operation. One interface processor is dedicated to task-synchronous data transfer while another handles continuous data transfer, allowing them to operate at different cycle rates without interfering with each other. This segmentation resolves the contradiction by enabling both synchronized and high-speed data transfer paths simultaneously.
Solution Approach 2:
The system implements dynamic cycle rate configuration where different interface processors can operate at different cycle rates according to their specific requirements. The task-synchronous interface processor operates at the task's cycle rate, while the continuous data transfer interface processor operates at a higher cycle rate to capture high-frequency sensor signals, thus adapting the system's timing characteristics to different data transfer needs.
2Device complexity
If a single interface processor is used for both task-synchronous and continuous data transfer, then device complexity is reduced, but latency and jitter increase
Solution Approach 1:
The interface unit is divided into multiple interface processors, each capable of independent operation. One interface processor is dedicated to task-synchronous data transfer while another handles continuous data transfer, allowing them to operate at different cycle rates without interfering with each other. This segmentation resolves the contradiction by enabling both synchronized and high-speed data transfer paths simultaneously.
Solution Approach 2:
A memory interface serves as an intermediary between the interface processors and the central processor. It manages the data flow from multiple interface processors operating at different cycle rates, buffering and forwarding data to the central processor without requiring the central processor to be directly involved in the high-frequency data transfer operations, thus reducing latency and jitter.
3Measurement precision
If interface processors operate at different cycle rates, then high-frequency signals are sampled accurately, but managing parallel data flows increases system complexity
Solution Approach 1:
The interface unit is divided into multiple interface processors, each capable of independent operation. One interface processor is dedicated to task-synchronous data transfer while another handles continuous data transfer, allowing them to operate at different cycle rates without interfering with each other. This segmentation resolves the contradiction by enabling both synchronized and high-speed data transfer paths simultaneously.
Solution Approach 2:
The system allows different cycle rate parameters to be configured for different interface processors based on their specific requirements. The task-synchronous interface processor operates at the task's cycle rate, while the continuous data transfer interface processor operates at a higher cycle rate to capture high-frequency sensor signals, thus adapting the system's timing characteristics to different data transfer needs.
4Productivity
If continuous data transfer is implemented independently of task cycle rate, then streaming capability is improved, but integration with task processing becomes difficult
Solution Approach 1:
The interface unit is divided into multiple interface processors, each capable of independent operation. One interface processor is dedicated to task-synchronous data transfer while another handles continuous data transfer, allowing them to operate at different cycle rates without interfering with each other. This segmentation resolves the contradiction by enabling both synchronized and high-speed data transfer paths simultaneously.
Solution Approach 2:
Both interface processors write to the same memory space and can be configured to handle different types of data transfer requirements. The system provides a universal interface that can accommodate both task-synchronous and continuous data transfer modes, allowing the same hardware architecture to serve multiple purposes through software configuration rather than requiring separate dedicated hardware paths.
Data Source
AI summary
A number of software routines comprising at least two software routines are created for an interface unit of a computer system having a first and a second interface processor for forwarding input data from a peripheral to a processor of the computer system on which software is programmed. A first subset of the software routines is assigned to a first category provided for task-synchronous data transfer, and a second subset of the software routines are assigned to a second category provided for continuous data transfer. The first interface processor is programmed with the first subset and the second interface processor with the second subset of software routines. During execution of the software, the first subset is cyclically executed by the first interface processor at a first cycle rate, and the second subset is cyclically executed by the second interface processor at a second cycle rate.