Interface Wafer Carrier for 3D IC Stacking Alignment
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Solution Overview
Problem
The fabrication of 3D integrated circuit devices faces challenges in achieving controlled substrate thickness for high-density through-silicon vias and multi-layer stacking, with existing techniques either increasing manufacturing costs, inducing yield loss, or degrading precision optical alignment due to the use of temporary handle wafers.
Innovation Solution
The method involves using an interface wafer as a permanent carrier for stacking layers, allowing for precise alignment and controlled substrate thinning without the need for temporary handle wafers, and utilizing through-silicon vias filled with tungsten or copper for efficient signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If temporary handle wafers are used for stacking layers, then flexibility in stacking configurations is improved, but precision optical alignment is degraded due to overlay distortions
Solution Approach 1:
The patent introduces a carrier wafer as an intermediary substrate that enables flexible stacking of multiple active circuitry layers without using temporary handle wafers. The carrier wafer serves as a stable base that maintains precision optical alignment while allowing adaptable stacking configurations of different layer types (logic, memory, RF).
Solution Approach 2:
The patent segments the stacking process into distinct stages: first bonding active circuitry layers to the carrier wafer, then bonding the stacked structure to the logic wafer. This segmentation allows the carrier wafer to provide stability during alignment-critical steps while enabling flexibility in the stacking sequence and configuration.
2Ease of manufacture
If direct face-to-face joining of wafers is used, then manufacturing simplicity is improved, but the logic wafer must undergo multiple bonding and thinning steps increasing the risk of catastrophic failure
Solution Approach 1:
The carrier wafer acts as a mediator that absorbs the complexity of multiple bonding and thinning steps. Instead of repeatedly bonding to and thinning the logic wafer, the process bonds active circuitry layers to the carrier wafer first, then bonds the complete stacked structure to the logic wafer in a single step, eliminating the risk of logic wafer failure during intermediate steps.
Solution Approach 2:
The patent performs preliminary bonding of active circuitry layers to the carrier wafer before final assembly with the logic wafer. This preliminary action completes the stacking process on a sacrificial carrier that protects the logic wafer from exposure to multiple processing steps that could cause catastrophic failure.
3Ease of manufacture
If general purpose substrate thinning techniques are used, then manufacturing cost is reduced, but controlled substrate thickness cannot be achieved for high-density through-silicon vias
Solution Approach 1:
The carrier wafer is a disposable, low-cost substrate that is intentionally designed to be removed after serving its purpose. It enables precise thickness control and via formation during the stacking process, then is selectively removed without affecting the final product cost since it is discarded after fulfilling its temporary function.
Solution Approach 2:
The patent changes the substrate thickness parameter by bonding thin active circuitry layers to the carrier wafer and then selectively removing portions of the carrier wafer. This allows precise control of the final substrate thickness and creates the necessary conditions for high-density through-silicon vias with reasonable aspect ratios.
4Manufacturing precision
If buried oxide layer is used as etch stop, then silicon-on-insulator wafers can be thinned controllably, but the technique does not work for circuits with structures extending below the buried oxide
Solution Approach 1:
The carrier wafer is a temporary, disposable substrate that replaces the buried oxide etch stop approach. It enables controlled thinning and via formation for all circuit structures without requiring specific features like buried oxide layers or double-BOX structures, making the technique universally applicable to different circuit architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-precision alignment and cost-effective fabrication of 3D integrated circuit structures with improved via density and reduced risk of catastrophic failure, maintaining the integrity of the logic wafer while allowing for flexible stacking configurations.
Implementation Method 1
the first active circuitry layer wafer is bonded face down to the interface wafer
Implementation Method 2
the interface wafer is thinned so as to form an interface layer
Implementation Method 3
metallizations are formed on the interface layer. The metallizations are coupled through the through-silicon vias
Data Source
AI summary
A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.