Interfacial Layer Etch-Back for High-k Gate Stack Scaling
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Solution Overview
Problem
Existing methods for forming interfacial layers in high-k and metal gate stacks are insufficient to meet the reduced equivalent oxide thickness (EOT) requirements for advanced semiconductor technologies beyond 45 nm, particularly for 32 nm technology, where the previous methods fail to scale down the capacitive effective thickness (CET) and introduce OH termination bonding issues.
Innovation Solution
The method involves forming high-quality interfacial layers with abundant OH bonding, such as ozonated films, and then etching them back to a thickness of no more than 0.7 nm, followed by UV curing or low-temperature annealing to densify the layer, allowing for subsequent high-k film deposition without significant thickening, thereby reducing the capacitive effective thickness of the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods (chemical oxide, ISSG, RTO) are used to form interfacial layers, then the interface between silicon surface and gate insulator is formed, but the equivalent oxide thickness (EOT) cannot be reduced below 0.8-1.0 nm
Solution Approach 1:
The patent applies preliminary action by forming a thicker interfacial layer (1.5-3 nm) before high-k dielectric deposition, then selectively removing excess oxide through etch-back or moisture treatment. This preliminary formation of abundant oxide ensures sufficient OH bonding sites are available before the final thinning process, resolving the contradiction between achieving thin EOT and maintaining interface quality.
Solution Approach 2:
The patent changes the parameter of interfacial layer thickness from the conventional 0.8-1.0 nm limit to a two-stage process: first forming 1.5-3 nm with abundant OH bonding, then reducing to 0.6-1.2 nm EOT through selective removal. This parameter transformation enables both thin final EOT and sufficient OH bonding for high-k film deposition.
2Ease of manufacture
If HF-based pre-clean processes are used, then cleaning is effective, but OH termination bonding is removed which is necessary for high-k film deposition
Solution Approach 1:
The patent performs preliminary oxide formation (1.5-3 nm) with abundant OH bonding before high-k deposition. This preliminary action ensures that even if subsequent cleaning processes remove some OH groups, sufficient bonding sites remain for successful high-k film deposition, while still allowing effective cleaning to occur.
Solution Approach 2:
The patent creates a cushion of excess oxide (1.5-3 nm initial thickness) that compensates for OH bonding loss during cleaning processes. This beforehand cushioning ensures that after cleaning and selective removal, the final interfacial layer (0.6-1.2 nm EOT) retains sufficient OH bonding for high-k deposition while having undergone effective cleaning.
3Length of moving object
If CET is reduced for scaling, then device density increases, but interface quality and OH bonding availability deteriorate
Solution Approach 1:
The patent forms the interfacial layer with thickness (1.5-3 nm) greater than the final required EOT (0.6-1.2 nm) before high-k deposition. This preliminary thicker formation ensures abundant OH bonding is available during the critical deposition phase, then excess oxide is selectively removed to achieve the target thin CET while preserving interface quality.
Solution Approach 2:
The patent applies local quality by creating different oxide thicknesses at different stages: initially forming uniform thick oxide (1.5-3 nm) for abundant OH bonding, then selectively thinning to varying degrees in different regions or layers to achieve final EOT of 0.6-1.2 nm, ensuring each location has appropriate thickness for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively scales down the CET of the gate stack, meeting the EOT requirements for 32 nm technology and beyond, while maintaining good film uniformity and preventing OH bonding issues during high-k film deposition.
Implementation Method 1
forming high-quality interfacial layers with abundant OH bonding, such as ozonated films
Implementation Method 2
UV curing or low-temperature annealing to densify the layer
Implementation Method 3
UV curing or low-temperature annealing to densify the layer
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.