Interfacial Layer for III-V HEMT Passivation
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Solution Overview
Problem
III-N HEMT devices face performance degradation due to lattice mismatch and strain between materials, leading to band distortion and electron trapping, which affects the device's turn-on/off performance and carrier mobility, with existing passivation layers causing impurity diffusion and damage during growth processes.
Innovation Solution
Incorporating an interfacial layer of III-V material between the bulk passivation layer and the device layer to prevent impurity diffusion, improve lattice matching, and reduce damage, thereby forming a high-quality bulk passivation layer that minimizes strain and enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a bulk passivation layer is deposited directly on the III-V device layer, then the device structure is simpler and manufacturing is easier, but impurity diffusion and damage occur during the growth process
Solution Approach 1:
An interfacial layer of III-V material is introduced between the bulk passivation layer and the device layer. This intermediary layer prevents direct contact between the passivation layer and device, blocking impurity diffusion and damage while allowing the passivation layer to perform its function. The interfacial layer acts as a protective barrier that resolves the contradiction between ease of manufacture and device reliability.
2Device complexity
If existing passivation layers are used, then the device structure is complete, but lattice mismatch and strain cause band distortion and electron trapping
Solution Approach 1:
The interfacial layer is specifically designed with III-V material composition that matches the device layer's lattice structure. This local quality adjustment at the critical interface region prevents lattice mismatch and strain, while the bulk passivation layer maintains its insulating properties. The solution addresses manufacturing precision by optimizing the local material properties where they are most needed.
3Productivity
If the passivation layer is grown directly on the device layer, then the process is faster and more efficient, but threshold voltage non-uniformity increases
Solution Approach 1:
The interfacial layer is formed preliminarily before depositing the bulk passivation layer. This preliminary action prepares the surface with appropriate lattice matching and reduces defects that would otherwise cause threshold voltage non-uniformity. By performing this preparation step in advance, the subsequent passivation layer growth can proceed efficiently while achieving uniform device characteristics.
Data Source
AI summary
The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.