Interference-Suppression Capacitors for Electronics Assembly
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Solution Overview
Problem
Conventional electronics assemblies face significant interference issues due to stray capacitances and inductances, which conventional interference-suppression capacitors often exacerbate by introducing additional stray inductance, making it difficult to effectively reduce common-mode and differential interferences.
Innovation Solution
The solution involves replacing single interference-suppression capacitors with multiple subcapacitors connected in parallel and arranged on a conductor structure, reducing stray inductance and enhancing the total capacitance, allowing for a low-inductance construction that effectively shields interferences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional interference-suppression capacitors are used to reduce common-mode interferences, then interference suppression is improved, but stray inductance increases
Solution Approach 1:
The single interference-suppression capacitor is divided into multiple subcapacitors (at least two) that are connected in parallel. Each subcapacitor has its own terminal connection to the DC link, creating multiple independent current paths. This segmentation reduces the total stray inductance because the inductances of parallel paths add reciprocally (1/L_total = 1/L1 + 1/L2 + ...), while the total capacitance adds directly (C_total = C1 + C2 + ...), thus improving interference suppression without significantly increasing stray inductance.
Solution Approach 2:
The patent introduces a spatial dimension to the capacitor configuration by arranging multiple subcapacitors at different locations on the conductor structure, each connected to different terminals of the DC link. This multi-dimensional arrangement creates multiple parallel current paths through space, reducing the loop area and associated stray inductance while maintaining effective interference suppression across different frequency ranges.
2Object-affected harmful factors
If external stray capacitances are reduced by minimizing output stray capacitance C1, then interference is reduced, but external stray capacitances C4 and C5 dominate and remain significant
Solution Approach 1:
The patent changes the parameter of total capacitance by combining multiple subcapacitors in parallel, creating a much larger total capacitance value that can effectively counteract the dominant external stray capacitances C4 and C5. This parameter change allows the interference suppression mechanism to remain effective even when external capacitances are significant, without requiring minimization of the output stray capacitance C1.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces interferences caused by stray inductances and capacitances, providing a more effective shielding of interferences compared to conventional approaches, without the need for equalizing stray capacitances C2 and C3.
Implementation Method 1
interference-suppression capacitors, which the electronics assembly or a unit connected to the electronics assembly has with respect to ground or with respect to a heat sink
Implementation Method 2
the heat sink is connected in an electrically conducting manner to the second conductor strip
Implementation Method 3
providing a more effective shielding of interferences compared to conventional approaches
Data Source
AI summary
An electronics assembly includes a plurality of first semiconductor chips each having a first load terminal and a second load terminal, a conductor structure having a first conductor strip, a second conductor strip and a third conductor strip, a plurality of first interference-suppression capacitors arranged on the conductor structure and each having a first capacitor terminal and a second capacitor terminal, and a heat sink. The first load terminal of each first semiconductor chip is electrically connected to the first conductor strip, the second load terminal of each first semiconductor chip is electrically connected to the third conductor strip, the first capacitor terminal of each first interference-suppression capacitor is electrically connected to the first conductor strip, the second capacitor terminal of each first interference-suppression capacitor is electrically connected to the second conductor strip, and the heat sink is electrically connected to the second conductor strip.