Intergate Spacer Layout for Stacked Transistor Pinch-Off Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing stacked transistor structures in integrated circuit devices face performance degradation due to recessed or pinched-off regions formed during the formation of work function layers, which affect the lower transistor's performance.
Innovation Solution
The integrated circuit device includes a stacked transistor structure with an upper transistor and a lower transistor, where an intergate spacer made of insulating material is placed adjacent to the side surface of the lower channel region, and a lower work function layer is formed between the lower channel region and the intergate spacer, followed by the deposition of an upper work function layer to reduce recessed or pinched-off regions and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked transistor structure is formed to increase integration density, then the integration density is improved, but recessed or pinched-off regions are formed during work function layer formation which degrade the lower transistor performance
Solution Approach 1:
An intergate spacer is introduced as an intermediary structure between the lower channel region and the upper gate. This spacer prevents direct contact and eliminates the formation of recessed or pinched-off regions in the lower transistor while maintaining the stacked configuration for high integration density
Solution Approach 2:
The intergate spacer is formed preliminarily before depositing the work function layer and gate structures. This preliminary action creates a protective barrier that prevents subsequent processing steps from causing damage to the lower transistor channel region
2Ease of manufacture
If work function layers are deposited in the stacked transistor structure, then the transistor functionality is achieved, but recessed or pinched-off regions are formed that affect lower transistor performance
Solution Approach 1:
The intergate spacer serves as a mediator that allows work function layers to be deposited for achieving transistor functionality while preventing these deposition processes from creating harmful recessed or pinched-off regions in the lower transistor
3Area of stationary object
If multiple transistors are vertically stacked, then the integration density is increased, but the lower transistor performance is degraded due to process interference
Solution Approach 1:
The stacked transistor structure is segmented by the intergate spacer, which divides the vertical stack into distinct regions. This segmentation isolates the lower transistor from process interference while maintaining the compact vertical arrangement for high integration density
Solution Approach 2:
The intergate spacer acts as an intermediary barrier between the lower and upper transistors, preventing process interference from the upper transistor formation steps from affecting the lower transistor performance
Data Source
AI summary
An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.