Interior Macro Pin Timing Updates Without Parent Timing Runs
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Solution Overview
Problem
Existing methods for timing constraints in integrated circuits (ICs) do not efficiently modify timing constraints for interior pins of macros during synthesis, requiring multiple iterations and parent timing runs, which is inefficient and time-consuming.
Innovation Solution
The method involves determining the distance moved by interior pins within a macro during synthesis and calculating updated timing constraints based on the metal layer associated with the unit, without requiring further iterations or parent timing runs, using lookup tables for RC delay and capacitance load adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional timing constraint methods are used for interior pins of macros during synthesis, then timing accuracy can be maintained, but the number of iterations and parent timing runs increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing RC delay and capacitance load values in lookup tables before synthesis begins. When interior pins move during synthesis, the method directly retrieves pre-computed timing values from these tables based on pin movement distance, avoiding the need for repeated iterative timing analyses. This preliminary preparation enables immediate timing constraint updates without triggering additional synthesis iterations or parent timing runs.
2Reliability
If multiple iterations and parent timing runs are performed to settle timing assertions, then timing constraints can be accurately satisfied, but the design turnaround time increases
Solution Approach 1:
The patent uses copying by creating lookup tables that contain pre-computed RC delay and capacitance load values representing timing characteristics. Instead of performing repeated iterative timing analyses, the method copies relevant timing data from these lookup tables based on the distance interior pins move from their original locations. This copying approach provides accurate timing constraint updates instantaneously, eliminating the need for multiple synthesis iterations and parent timing runs while maintaining timing constraint satisfaction.
3Productivity
If timing constraints are not updated for moved pins, then synthesis runs faster, but timing assertions cannot be properly settled
Solution Approach 1:
The patent introduces an intermediary mechanism consisting of lookup tables that store pre-computed RC delay and capacitance load values. When interior pins move during synthesis, the method uses these lookup tables as intermediaries to quickly determine updated timing constraints based on pin movement distance. This intermediary approach enables the synthesis tool to efficiently update timing constraints without performing full iterative timing analyses, thereby maintaining both synthesis speed and timing assertion accuracy.
Data Source
AI summary
Embodiments are for using out-of-context timing constraints modification for pins of a macro an integrated circuit (IC). A technique includes moving at least one pin of a macro during synthesis for the IC, in response to performing synthesis on a specification for the IC and determining a distance that the at least one pin moved from an original location to a new location in the macro. The technique includes determining a delay based at least in part on the distance moved and using the delay to determine a signal timing at the least one pin at the new location in the macro.