Interior Polygonal Pads for Semiconductor Package Density
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Solution Overview
Problem
As the size of flat no-lead semiconductor packages decreases, maintaining adequate space between pads to prevent electric interference while ensuring sufficient pad surface area for reliable physical and electrical connections to printed circuit boards becomes a challenge.
Innovation Solution
The use of interior polygonal pads, such as triangular and trapezoidal pads, arranged to maximize separation distances with a large pitch exceeding 0.4 mm and separation distances of around 0.2 mm, ensuring no shorting while providing enough surface area for reliable connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of flat no-lead packages is decreased, then packaging density is improved, but adequate space between pads to prevent electric interference deteriorates
Solution Approach 1:
The patent transitions from conventional outer lead arrangements to interior pads located on the bottom surface of the package. This dimensional repositioning allows pads to be arranged in a more optimized spatial configuration, increasing separation distances between adjacent pads while maintaining compact package dimensions. The interior pad layout on the bottom surface enables better control over pad-to-pad spacing, preventing electric interference even as package size decreases.
2Object-affected harmful factors
If pad separation distance is increased to prevent shorting, then electric interference is reduced, but pad surface area for reliable connections deteriorates
Solution Approach 1:
The patent employs different pad geometries (triangular, rectangular, trapezoidal) optimized for specific locations within the package. Interior pads positioned away from edges can utilize larger surface areas, while edge pads have reduced dimensions. This localized optimization ensures that each pad has sufficient surface area for reliable electrical connections while maintaining adequate separation distances from adjacent pads, preventing shorting conditions.
Data Source
Figure 1A~1B
Figure 2~3A
Figure 3B~3C
AI summary
Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.