Semiconductor Package Spacer Layout to Prevent Substrate Cracks
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Solution Overview
Problem
Conventional semiconductor packages face challenges in reducing stress on substrates due to misalignment of spacer side surfaces with semiconductor chip side surfaces, leading to potential cracks in internal interconnection lines.
Innovation Solution
The semiconductor package design includes a spacer with side surfaces positioned more interiorly than the semiconductor chips, reducing stress on the substrate by using a spacer with a smaller footprint than the semiconductor chips, and employing adhesive layers and a mold layer to secure the components, thereby preventing crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the spacer side surfaces are aligned with the semiconductor chip side surfaces, then the manufacturing process is simplified, but stress concentrates on the substrate causing cracks in internal interconnection lines
Solution Approach 1:
The spacer is designed with an asymmetric position relative to the semiconductor chip, where the spacer's side surfaces are intentionally positioned more interiorly than the chip's side surfaces. This asymmetric arrangement creates a stress-distributing configuration that prevents concentration of stress at the substrate level, thereby preventing cracks in internal interconnection lines while maintaining manufacturing feasibility.
Solution Approach 2:
The spacer acts as a cushioning element positioned between the semiconductor chip and the substrate. By placing the spacer's side surfaces more interiorly than the chip's side surfaces, the structure beforehand cushions and distributes the stress that would otherwise concentrate on the substrate during thermal expansion or mechanical loading, preventing crack formation in the internal interconnection lines.
2Quantity of substance
If the spacer has the same footprint as the semiconductor chip, then material usage is optimized, but stress on the substrate increases leading to potential cracks
Solution Approach 1:
The spacer is designed with non-uniform local quality in terms of its lateral dimensions. Specifically, the spacer's width and length are made smaller than those of the semiconductor chip, creating a localized stress-relief zone. This local quality difference allows the spacer to fulfill its support function while simultaneously reducing the overall stress transmitted to the substrate, preventing crack formation.
3Reliability
If the spacer side surfaces are positioned more interiorly than the semiconductor chip side surfaces, then stress on the substrate is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The spacer's reduced dimensions and interior positioning are predetermined in the design stage, allowing for preliminary action in stress distribution. By pre-configuring the spacer with smaller width and length than the chip, the stress distribution pattern is established before assembly, reducing the need for high-precision adjustments during manufacturing while maintaining substrate stability.
Data Source
AI summary
A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip. The stack of second semiconductor chips has a lateral footprint greater than the lateral area of the first portion of the surface of the substrate so that at least a portion of the stack of second semiconductor chips overhangs at least one sidewall of at least one of the spacer and the first semiconductor chip, which extend between the stack of second semiconductor chips and the surface of the substrate.