Interlace Video Signal Control for LCD Residual Image Prevention

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Solution Overview

Problem

IPS liquid crystal displays face challenges in preventing residual image phenomena, especially with interlace videos, due to charge accumulation caused by impurities and polarity differences between odd and even fields, which existing technologies struggle to address effectively.

Innovation Solution

A video processing device that generates a display video signal for a liquid crystal display using a frame inversion scheme, with a control microcomputer setting a display invalid section for interlace video signals based on a vertical synchronization signal, and optionally adjusting this period based on temperature detection, to prevent charge accumulation and residual images.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If interlace video is displayed using frame inversion scheme, then view angle characteristics are improved, but residual image phenomenon occurs due to charge accumulation

Engineering Contradiction:
Improveview angle characteristicsVSAvoidresidual image phenomenon
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent applies periodic action by inverting the polarity of the liquid crystal display at regular intervals (every N frames) to eliminate charge accumulation. The control microcomputer controls the data enable signal to set display invalid sections at periodic intervals, creating a periodic polarity inversion that prevents residual image formation while maintaining the benefits of frame inversion driving scheme for view angle characteristics.

Inventive Principle:
Principle #19Periodic action

2Reliability

If polarity inversion is conducted for each frame, then charge accumulation is eliminated for non-interlace video, but charge accumulation cannot be eliminated for interlace video due to field polarity differences

Engineering Contradiction:
Improvecharge accumulation eliminationVSAvoidcompatibility with interlace video
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the display invalid section setting adaptable to different video types. The control microcomputer detects whether the input video is interlace or non-interlace and dynamically adjusts the polarity inversion strategy: for non-interlace video, it uses standard frame-by-frame polarity inversion, while for interlace video, it sets display invalid sections at periodic intervals to achieve effective polarity inversion despite field differences.

Inventive Principle:
Principle #15Dynamics

3Reliability

If display invalid section is set at fixed period, then residual image phenomenon is prevented, but temperature changes affect prevention effectiveness

Engineering Contradiction:
Improveresidual image preventionVSAvoidtemperature adaptation
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent applies feedback by using a temperature detector to monitor the display device temperature and feeding this information back to the control microcomputer. The control microcomputer then adjusts the display invalid section period based on the detected temperature, extending the period at higher temperatures and reducing it at lower temperatures to maintain optimal residual image prevention effectiveness across different operating conditions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10462335B2Video processing device
Publication Date: 2019.10.29 FUJITSU TEN LTD
  • US10462335B2 patent drawing
  • US10462335B2 patent drawing
  • US10462335B2 patent drawing

AI summary

Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.