Interlaced 3D Inductor Structure for High Inductance Density

The patent transitions from planar 2D coil structures to three-dimensional stacked coil structures with vertical interconnections. Multiple coil layers are stacked above each other and connected through vertical conductive vias, creating a 3D inductor that achieves higher inductance density and better performance without proportionally increasing the planar footprint area.

The patent implements nested coil structures where inner coils are positioned within the geometric center of outer coils, and multiple coil layers are stacked vertically with interconnections. This nested arrangement maximizes the use of available space, increases effective inductance, and reduces the overall area required while maintaining electromagnetic performance.

By stacking coils in multiple vertical layers and connecting them through vertical vias, the patent creates a three-dimensional structure that separates current paths in the vertical dimension. This reduces the planar overlap between adjacent conductors, thereby reducing parasitic capacitance while maintaining inductance through the stacked configuration.

The inductor is divided into multiple separate coil layers stacked vertically, with each layer being an independent conductive structure. The layers are connected through discrete vertical interconnection vias rather than continuous planar traces, which segments the current path and reduces unwanted capacitive coupling between adjacent conductive elements.

The patent employs asymmetric coil winding patterns within each layer, where inner coils are positioned at the geometric center of outer coils. This deliberate asymmetric nested configuration optimizes magnetic flux distribution and increases mutual inductance between coils, thereby enhancing the quality factor while the overall stacked structure maintains rotational symmetry for interference rejection.

Coils are arranged in nested configurations where smaller inner coils are positioned within the center of larger outer coils. This nested arrangement maximizes magnetic coupling and mutual inductance between coils, improving the quality factor. The nested structure also maintains compact geometry that can preserve overall symmetry when stacked in multiple layers.

The patent adds the vertical dimension by stacking multiple coil layers above each other and connecting them through vertical conductive vias. This three-dimensional configuration increases the effective inductance within a given planar footprint, achieving higher inductance density without requiring proportionally more complex planar patterns. The vertical stacking leverages the third dimension to pack more inductance into the same chip area.

Multiple coil layers are stacked vertically with inner coils nested within outer coils in each layer. This nested stacked configuration maximizes the use of available vertical and planar space, increasing the effective number of turns and inductance value within a compact footprint. The nested arrangement ensures efficient space utilization while maintaining manufacturability through standard semiconductor fabrication processes.