3D Memory Contact Region Interlacing for Denser Array Layouts
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently integrating separated contact regions that are laterally spaced apart, which affects the overall performance and density of the memory arrays.
Innovation Solution
A semiconductor structure with a memory die is developed, featuring an alternating stack of insulating layers and electrically conductive layers that laterally extend through multiple regions, including memory array regions and contact regions. This structure includes arrays of memory openings filled with vertical stacks of memory elements, and methods for forming this structure involve forming alternating stacks, memory openings, and fill structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If contact regions are laterally spaced apart in three-dimensional memory devices, then integration efficiency and memory array density are improved, but the complexity of forming separated contact regions increases
Solution Approach 1:
The contact regions are divided into separate, laterally spaced apart regions rather than being continuous. This segmentation allows independent formation and integration of contact regions with memory array regions, improving density while managing complexity through modular construction
Solution Approach 2:
The patent transitions from two-dimensional planar contacts to three-dimensional vertically extended contacts. By stacking contact regions vertically above memory array regions and using alternating insulating and conductive layers, the design achieves higher density without increasing lateral footprint, resolving the contradiction between density and formation complexity
2Quantity of substance
If alternating stacks of insulating and conductive layers are used to form memory structures, then memory element density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Insulating layers serve as intermediary elements between conductive layers, providing electrical isolation and structural support. This intermediary approach enables precise stacking of conductive layers at different lateral positions without electrical interference, achieving high density while managing manufacturing precision through controlled alternating deposition
Solution Approach 2:
The patent varies the lateral extent parameters of conductive layers relative to insulating layers in the alternating stack. By controlling which layers extend further laterally, the design achieves different functional regions (memory array vs. contact regions) with precise material deposition, improving density while managing precision through parameter control rather than complex geometry
3Adaptability or versatility
If contact regions are formed within the alternating stack structure, then device integration is improved, but the difficulty of forming separated contact regions increases
Solution Approach 1:
The alternating stack of insulating and conductive layers serves multiple functions simultaneously: it forms memory elements in some regions and contact regions in others. This universal structure eliminates the need for separate formation processes for contacts and memory elements, improving integration while reducing overall formation difficulty through process consolidation
Solution Approach 2:
The alternating stack structure is formed preliminarily before defining specific contact regions. By establishing the layered framework first, subsequent contact region formation becomes simpler as it only requires selective patterning and filling in predefined zones, rather than creating contacts from scratch, thus improving integration while managing formation difficulty
Data Source
AI summary
A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.