Interlaced Diode Layout for Junction Perimeter Expansion
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Solution Overview
Problem
The increasing power consumption of electronic devices leads to higher driving currents in diodes, necessitating an increase in diode area to enhance the effective junction perimeter, which poses a challenge in efficient area enlargement.
Innovation Solution
A semiconductor device layout featuring interlaced first and second wires forming closed polygons around a center, with additional wires radially extending and interlaced, coupled at specific points to prevent short circuits and optimize area utilization, while being electrically connected to P-type and N-type doping layers to function as anode and cathode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the area of the diode is increased to enlarge the effective junction perimeter, then the power handling capability is improved, but the area occupation increases
Solution Approach 1:
The diode structure is segmented into multiple fingers (anode fingers and cathode fingers) that are interlaced with each other. This segmentation allows the current to flow through multiple parallel paths, effectively increasing the total junction perimeter without requiring a proportional increase in the overall diode area. The segmented finger structure enables more efficient utilization of the available area.
Solution Approach 2:
The patent transitions from a conventional planar diode structure to a three-dimensional interlaced finger configuration. By stacking anode and cathode fingers in an interlaced manner, the design utilizes vertical and lateral dimensions simultaneously, creating multiple current paths that increase the effective junction perimeter while maintaining a compact footprint area.
2Area of moving object
If more wires are added to increase junction perimeter, then the effective area is enlarged, but the device complexity increases
Solution Approach 1:
The patent merges the anode and cathode finger structures into a single interlaced configuration where both sets of fingers are formed simultaneously or in an integrated manner. This merging approach allows multiple current-carrying elements to share the same spatial envelope, increasing the junction perimeter while avoiding the complexity of separate, independently routed wire structures.
Solution Approach 2:
The interlaced finger structure serves multiple functions simultaneously: it provides current conduction paths, defines the junction perimeter, and maintains mechanical support. This multi-functionality reduces the need for additional specialized components or structures, thereby limiting the increase in device complexity despite the increased junction perimeter.
Data Source
AI summary
A semiconductor device includes a plurality of first wires and a plurality of second wires. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires is forming the closed polygon and surrounding the center. The first and second wires are interlaced, and none of the first wires and second wires are coupled to each other.