Interlaced Diode Wire Layout for Junction Perimeter
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to reduced diode junction perimeter, limiting driving current, and existing methods struggle to efficiently increase this perimeter without enlarging the device area.
Innovation Solution
A semiconductor device layout featuring interlaced first and second conductive wires forming closed polygons or ellipses around a center, with conductive layers disposed between and covering these wires, increasing junction perimeter and driving current without area expansion, and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device area is miniaturized, then the device size is reduced, but the diode junction perimeter decreases
Solution Approach 1:
The patent transitions from planar wire arrangements to three-dimensional stacked conductive layers. Multiple conductive layers are positioned at different vertical levels (Z-dimension) with interlaced wire patterns, allowing the junction perimeter to extend into the third dimension. This vertical stacking enables increased junction perimeter while maintaining a compact footprint area.
Solution Approach 2:
The patent implements nested interlaced patterns where conductive wires in different layers are positioned to interlace with wires in adjacent layers. The wires form nested closed-loop patterns where inner loops are surrounded by outer loops across multiple layers, maximizing the junction perimeter within the constrained device area by utilizing both horizontal and vertical spatial relationships.
2Power
If the junction perimeter is increased to enhance driving current, then the driving current increases, but the device area must be enlarged
Solution Approach 1:
The patent resolves this contradiction by extending the junction perimeter into the vertical dimension through stacked conductive layers. The interlaced wire patterns across multiple layers create additional junction paths without requiring proportional increases in planar area. This enables higher driving current while maintaining a compact device footprint.
Solution Approach 2:
The patent combines multiple conductive layers with interlaced wire patterns into a unified three-dimensional structure. The wires from different layers are positioned to interlace and form combined closed-loop patterns, effectively merging the junction paths across layers to maximize the total junction perimeter within the constrained device area.
3Device complexity
If conventional wire layouts are used, then the layout is simple, but the junction perimeter cannot be efficiently increased
Solution Approach 1:
The patent introduces vertical stacking of conductive layers to increase junction perimeter. While this adds structural complexity compared to single-layer layouts, the standardized interlaced patterns and systematic layer arrangement provide a scalable approach that efficiently generates extended junction perimeter without proportionally increasing overall device complexity.
Data Source
AI summary
A semiconductor device includes a plurality of first wires and second wires, a first conductive layer, and a second conductive layer. Each of the first wires forms a closed polygon and surrounds a center, and each of the second wires forms the closed polygon and surrounds the center. The first and second wires are interlaced, and none of the first and second wires are coupled to each other. The first conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the first wires. The second conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the second wires. The first conductive layer is disposed between the second conductive layer and the first and second wires, and the first and second conductive layers are not coupled to each other.