Interlaced Electrode Capacitor for Multilayer Circuit Board
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Solution Overview
Problem
Existing capacitors on multilayer circuit boards face challenges in increasing capacitance without wasting space by enlarging metal plates and maintaining impedance match by thickening the dielectric layer.
Innovation Solution
The capacitor design features four electrode layers with interlaced coupling portions and a dielectric layer configuration within a multilayer circuit board, allowing for increased capacitance without altering the capacitor's size and maintaining impedance match.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of the metal plate is increased to increase capacitance, then capacitance is improved, but space on the circuit board is wasted
Solution Approach 1:
The patent transitions from a single-layer capacitor structure to a multilayer electrode configuration. By stacking multiple electrode layers (first positive electrode layer, first negative electrode layer, second positive electrode layer, second negative electrode layer) with dielectric layers between them, the capacitor increases its effective plate area in the vertical dimension rather than expanding horizontally on the circuit board. This dimensional transition allows capacitance enhancement while maintaining compact footprint.
Solution Approach 2:
The patent embeds multiple electrode layers within each other in a nested configuration. The first and second positive electrode layers are positioned between the first and second negative electrode layers, creating an interlaced nested structure. This nesting arrangement maximizes the use of available vertical space, allowing multiple capacitive elements to occupy the same horizontal footprint while maintaining individual electrical isolation through dielectric layers.
2Quantity of substance
If the thickness of the dielectric layer is decreased to increase capacitance, then capacitance is improved, but impedance match of the circuit is affected
Solution Approach 1:
Instead of decreasing dielectric thickness to increase capacitance, the patent increases capacitance by adding more electrode layers in the vertical dimension. Each dielectric layer maintains its standard thickness for proper impedance matching, while the cumulative effect of multiple parallel capacitor structures (formed by the interlaced electrode layers) increases total capacitance. This approach decouples the capacitance enhancement from dielectric thickness reduction.
Solution Approach 2:
The patent combines multiple capacitor structures into a single integrated multilayer component. The first positive electrode layer with first negative electrode layer forms one capacitor, while the second positive electrode layer with second negative electrode layer forms another capacitor. These capacitors are electrically connected in parallel through the shared electrode structure, merging their capacitance values while each maintaining its own dielectric layer thickness for proper impedance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively enhances capacitance while conserving space on the circuit board and maintaining impedance match, optimizing the performance of capacitors in multilayer circuit boards.
Implementation Method 1
A capacitor may be located on a circuit board that includes two opposite metal plates and a dielectric layer positioned between the two opposite metal plates. Capacitance of the capacitor is proportional to area of the metal plate, and is inversely proportional to a thickness of the dielectric layer.
Implementation Method 2
a dielectric layer positioned between the two opposite metal plates
Data Source
AI summary
A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.