Interlaced Finger MOS Transistor for Current Distribution
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Solution Overview
Problem
Conventional MOS transistors face challenges in evenly distributing high currents, leading to uneven stress on individual transistors and increased parasitic losses at high frequencies, particularly in GSM signal transmission applications.
Innovation Solution
The MOS transistor structure features doped areas with parallel strip shapes, separated by gate regions, and conductive elements that interlace fingers connecting to both drains and sources, ensuring equal current distribution and minimizing capacitive coupling losses through a comb-shaped configuration and additional vias for improved current handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional MOS transistor structures are used to handle high currents, then current transmission capability is improved, but current distribution becomes uneven and parasitic losses increase
Solution Approach 1:
The transistor structure is divided into multiple elementary transistors arranged in parallel, with each transistor having its own dedicated conductive path. This segmentation ensures that current is evenly distributed across all transistors, preventing any single transistor from bearing excessive current load and reducing overall parasitic losses.
Solution Approach 2:
The conductive elements are designed with a three-dimensional interlaced finger configuration, where first and second conductive elements extend in alternating patterns above and between doped areas. This spatial arrangement in multiple dimensions creates balanced current paths of equal length, ensuring uniform current distribution while minimizing parasitic capacitance between conductive elements and substrate.
2Speed
If conventional MOS transistor structures are used for high-frequency operations, then signal transmission is enabled, but capacitive coupling losses increase
Solution Approach 1:
The conductive elements are positioned at different vertical levels and arranged in an interlaced finger pattern, creating spatial separation that minimizes parasitic capacitance between adjacent conductors. This three-dimensional configuration reduces capacitive coupling effects that would otherwise cause energy losses at high frequencies.
Solution Approach 2:
The symmetric interlaced configuration of conductive elements ensures that all current paths have equal length and equivalent electrical characteristics. This equipotential design minimizes voltage differences and capacitive coupling between adjacent conductors, reducing energy losses during high-frequency signal transmission.
3Power
If MOS transistors are designed to handle significant currents, then current capacity is improved, but series resistance increases
Solution Approach 1:
The transistor is segmented into multiple parallel elementary transistors, each contributing to the total current capacity. By distributing the current across multiple parallel paths, the overall series resistance is reduced according to the parallel resistance formula, allowing high current capacity while maintaining low resistance.
Solution Approach 2:
Multiple conductive elements are merged into a unified interlaced configuration that combines the current-carrying paths of all elementary transistors. This merging of parallel conductive paths creates low-resistance connections that can handle significant currents while minimizing total series resistance through the parallel combination effect.
Data Source
AI summary
A MOS transistor capable of withstanding significant currents, having doped areas corresponding to first and second main terminals of elementary MOS transistors and having, in top view, the shape of parallel strips separated by gate regions; first conductive elements which do not extend on the doped areas corresponding to the second main terminals and dividing into first fingers extending at least partly on the doped areas corresponding to the first main terminals and connected thereto; and second conductive elements which do not extend on the doped areas corresponding to the first main terminals and divide into second fingers extending at least partly on the doped areas corresponding to the second main terminals and connected thereto, the second fingers being at least partly intercalated with the first fingers.