Interlaced Gate Drive Circuit for Stable OLED Shift Register Output
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Solution Overview
Problem
Existing gate drive circuits experience unstable output due to suspended states in time sequences between interlaced lines, particularly in OLED designs, leading to poor shifting register stability.
Innovation Solution
A gate drive circuit with unit circuits comprising a control module, first and second clock terminals, logic turn-on input and output terminals, and gating modules, where the control module manages signal transmission based on clock terminal states to prevent suspended states by ensuring continuous signal input between interlaced lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an interlaced output structure is used in OLED gate drive circuits, then the display can be driven efficiently, but suspended states occur between line n and line n+2 causing output instability
Solution Approach 1:
The patent applies preliminary action by pre-charging nodes B and C before the interlaced output operation. Specifically, during the period when line n is being output, nodes B and C are pre-charged to appropriate voltage levels through transistors M23, M21, M22, M12, M20, and M19. This preliminary charging ensures that when the suspended state occurs between line n and line n+2, the nodes already have the correct voltage levels maintained, preventing instability in the shifting register output while maintaining the efficient interlaced display driving.
2Device complexity
If a simple three-clock control structure is used, then the circuit complexity is reduced, but the output stability deteriorates due to suspended states in interlaced operation
Solution Approach 1:
The patent maintains the simple three-clock control structure (CLK, CLKB, and the third clock signal) but adds preliminary action by introducing pre-charging phases. During specific clock periods, transistors M23, M21, M22, M12, M20, and M19 are activated to pre-charge nodes B and C before the actual data output. This approach preserves the low complexity of the three-clock system while ensuring output stability through the preliminary voltage establishment on critical nodes, preventing the suspended state from causing instability.
3Ease of operation
If nodes B and C are left in suspended state during interlaced output, then the circuit operation is simplified, but the remnant voltages interfere with each other affecting output stability
Solution Approach 1:
The patent applies the taking out principle by extracting and actively managing the voltage levels on nodes B and C during the interlaced output operation. Instead of allowing these nodes to remain in a passive suspended state, the circuit actively extracts and maintains the necessary voltage levels through dedicated transistor paths (M23-M22 for node B, and M21-M20 for node C). This active management removes the harmful remnant voltage interference while maintaining relatively simple circuit operation, as the same transistors used for data output also perform the voltage maintenance function.
Data Source
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AI summary
An embodiment of the present invention discloses a gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module. An embodiment of the present invention also provides a display device comprising the gate drive circuit. A gate drive circuit with interlaced output is realized, ensuring no suspended state in time sequence between interlaced lines, while maintaining an original dual time sequence (i.e., eliminating suspended state between interlaced lines, and ensuring a stable output of the shifting register).