Interlaced Gate Driving Circuits for Display Panel Opening Uniformity
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Solution Overview
Problem
Display panels with openings face challenges in driving pixels uniformly due to unilateral driving, leading to boundary phenomena caused by differing waveforms on either side of the opening, which results in distorted signals and a crossover effect.
Innovation Solution
A display panel configuration with interlaced gate driving circuits and signals, where the rise and fall times of gate signals are adjusted to ensure uniform signal delivery across the display areas, including a first and second display area with an opening, using first and second gate driving circuits that output signals to gate lines in an interlaced manner, with longer rise and fall times for the second gate signal to compensate for unilateral driving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If unilateral driving is used for display areas on both sides of the opening, then device complexity is reduced, but display quality deteriorates due to boundary phenomena and waveform differences
Solution Approach 1:
The patent applies different driving modes to different regions: interlaced driving for the first display area (above opening) and unilateral driving for the second display area (below opening). This local differentiation allows each region to be optimized independently, maintaining display quality while managing complexity
Solution Approach 2:
The patent adjusts the waveform parameters of gate signals specifically for the unilateral driving region. By modifying rise time and fall time of gate signals in the second display area, the waveform differences between near-end and far-end pixels are compensated, eliminating boundary phenomena while keeping the unilateral driving structure
2Manufacturing precision
If interlaced driving is used for all display areas, then display quality is improved with uniform waveforms, but device complexity increases due to dual gate driving circuits
Solution Approach 1:
The patent implements interlaced driving only in the first display area where it is most needed to prevent boundary phenomena, while using simpler unilateral driving in the second display area. This selective application reduces overall circuit complexity while maintaining display quality where critical
Solution Approach 2:
The display panel is divided into two distinct driving regions separated by the opening: the first display area uses interlaced driving with two gate driving circuits, while the second display area uses unilateral driving. This segmentation allows each region to use the most appropriate driving mode, balancing quality and complexity
3Manufacturing precision
If gate signal rise time and fall time are extended for unilateral driving, then signal uniformity is improved, but response speed deteriorates
Solution Approach 1:
The patent applies extended rise and fall times only to gate signals in the unilateral driving region (second display area), while maintaining standard signal timings in the interlaced driving region. This localized parameter adjustment achieves signal uniformity where needed without impacting overall response speed
Data Source
AI summary
A driving method, suitable for a display panel. The display panel includes a first display area, a second display area, a first gate driving circuit and a second gate driving circuit. The second display area comprises an opening. The driving method includes outputting a first gate signal to several first gate lines located at the first display area by the first gate driving circuit; outputting the first gate signal to several second gate lines located at the first display area by the second gate driving circuit, wherein the first gate lines and the second gate lines are arranged in an interlaced manner; outputting the first gate signal and a second gate signal to several third gate lines located at the second display area in the interlaced manner by the first gate driving circuit and the second gate driving circuit.


