Multilevel Interconnect Shielding with Interlaced Metal Patterns

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Solution Overview

Problem

The existing semiconductor manufacturing process for CMOS image sensors results in rugged and rough surfaces due to high pattern density in shielding metal layers, leading to dishing issues during metallization and planarization processes, which worsen with multiple processes.

Innovation Solution

A method of fabricating multilevel interconnects with an interlacing design, where patterned metal layers are formed with similar or same pattern densities to prevent surface roughness, and a planarized dielectric layer is deposited to maintain a flat surface, with additional metallizing processes allowing for better light shielding effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a metal pattern with large superficial measure is used as a shielding structure, then the shielding effect is improved, but the pattern density becomes much greater, causing dishing and surface roughness during planarization processes

Engineering Contradiction:

Improvelight shielding effectVSAvoidsurface flatness

Core Design Contradiction:

Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent divides the shielding function into multiple metal layers (first shielding metal layer and second shielding metal layer) with different pattern densities. The first shielding metal layer has higher pattern density for effective shielding, while the second shielding metal layer has lower pattern density to reduce dishing. This segmentation allows each layer to perform its specific function without compromising overall surface flatness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the shielding structure have different pattern densities optimized for their specific functions. The first shielding metal layer uses high pattern density in areas requiring strong shielding, while the second shielding metal layer uses lower pattern density to maintain surface quality. This local differentiation resolves the contradiction between shielding effectiveness and surface flatness.

Inventive Principle:

Principle #3Local quality

2Device complexity

If multiple metallization and planarization processes are performed, then the interconnect structure complexity is improved, but the surface roughness and dishing problems become more serious

Engineering Contradiction:

Improveinterconnect structureVSAvoidsurface flatness

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the shielding function across multiple layers rather than concentrating it in a single layer. The first shielding metal layer provides primary shielding with higher pattern density, while the second shielding metal layer provides additional shielding with lower pattern density. This segmentation distributes the dishing effect across layers, preventing cumulative surface degradation from multiple planarization processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent addresses surface flatness issues by moving the shielding function into the vertical dimension with multiple layers, rather than relying on a single planar layer. This dimensional transition allows the system to achieve both complex interconnect functionality and maintained surface quality through distributed shielding across different heights.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method prevents surface roughness and dishing issues, maintaining a flat surface even with multiple metallization and planarization processes, while providing effective light shielding by interlacing patterns of metal layers to cover the logical circuit area completely.

Implementation Method 1

The metallizing process includes etching the ILD layer 116

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

depositing a metal layer such as a copper metal layer on the ILD layer 116

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

performing a planarization process such as a chemical mechanical polishing (CMP) process on the metal layer and the ILD layer 116

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS8309453B2Multilevel interconnects structure with shielding function and fabricating method thereof

Publication Date: 2012.11.13 UNITED MICROELECTRONICS CORP

AI summary

A method of fabricating multilevel interconnects includes providing a substrate having a pixel array area and a logical circuit area, forming a first dielectric layer on the substrate, performing a first metallizing process on the first dielectric layer to form a first patterned metal layer and a second patterned metal layer above the pixel array area and the logical circuit area respectively, forming a second dielectric layer on the first patterned metal layer, the second patterned metal layer, and the first dielectric layer, performing a second metallizing process on the second dielectric layer to form a third patterned metal layer and a fourth patterned metal layer above the pixel array area and the logical circuit area respectively, wherein patterns of the fourth and the second patterned metal layer interlace to completely cover the logical circuit area, and depositing a dielectric layer on the third and the fourth patterned metal layer.