Interlaced PCB Traces and Vias for Crosstalk Control
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Solution Overview
Problem
In multi-layer printed circuit boards (PCBs), high-frequency signals can experience undesirable capacitive and inductive coupling between vias and traces, leading to noise and errors in computing systems.
Innovation Solution
The implementation of intermingled differential vias and a specific via and trace architecture that includes backdrilling and a ground-signal-signal-ground (GSSG) configuration to minimize crosstalk and optimize PCB real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vias and traces are placed near each other to reduce PCB area, then area utilization is improved, but capacitive coupling and crosstalk increase
Solution Approach 1:
The patent utilizes the vertical dimension by routing traces through different layers of the PCB stackup. Specifically, alternating traces are routed through adjacent layers (e.g., layer n and layer n+1), which separates them in the vertical dimension while allowing close spacing in the horizontal plane. This dimensional transition enables area-efficient layout while reducing capacitive coupling between adjacent traces.
Solution Approach 2:
The patent segments the PCB into multiple layers with specific routing patterns. By dividing the trace routing across multiple layers and using differential via structures (some vias extending fully through the stackup, others stopping at intermediate layers), the design creates electrical isolation between adjacent traces while maintaining compact footprint.
2Speed
If high-frequency signals are transmitted through vias and traces, then data processing speed is improved, but noise and errors increase due to crosstalk
Solution Approach 1:
The patent converts the potentially harmful capacitive coupling effect into a beneficial differential signaling mechanism. By arranging traces as differential pairs with equal and opposite signals, the design exploits the coupling effect to maintain signal integrity - the coupled noise appears equally on both differential lines and is rejected by the differential receiver, transforming the harmful coupling into a useful feature for noise immunity.
Solution Approach 2:
The patent changes the electrical parameters of the traces by implementing differential signaling with controlled impedance. The traces are designed with specific width, spacing, and layer positioning to control their electrical characteristics, ensuring that the differential mode signals maintain high-speed performance while common-mode noise is rejected.
3Adaptability or versatility
If more vias are added to connect layers, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different via structures to different locations in the PCB. Full-length vias are used where complete layer-to-layer connection is required, while partial-length vias (stopping at intermediate layers) are used where only selective connectivity is needed. This localized differentiation simplifies manufacturing by reducing the total number of full vias while maintaining necessary electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces crosstalk among multi-layer PCB structures, enabling faster data processing with reduced noise and errors, while also optimizing the use of PCB space.
Implementation Method 1
a signal transmitted along a via or trace may capacitively couple with/to another via or trace that is located nearby
Implementation Method 2
the higher the frequency of the signals, the higher, typically, is undesirable capacitive (and/or inductive) coupling and resulting errors
Data Source
AI summary
A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components.