Interlaced Row Driving for Extended Reset in Display Panels
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Solution Overview
Problem
In large display panels, the delay in scan driving circuits leads to insufficient reset duration for reset transistors, resulting in poor display quality due to incomplete black state achievement.
Innovation Solution
An interlaced row driving method is employed, where the output terminal of a gate register is connected to both the compensation control terminal and the reset control terminal of adjacent pixel driving circuits, extending the reset duration of the first reset transistor through staggered gate control signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display panel size is increased, then the display area is enlarged, but the scan driving circuit delay increases and reset duration becomes insufficient
Solution Approach 1:
The gate driving circuit is divided into multiple gate registers (first gate register, second gate register, etc.) that operate in an interlaced manner. Each gate register controls specific rows of pixel circuits, allowing the reset operation to be segmented across multiple time slots. This segmentation extends the effective reset duration by distributing the reset control signals across different time periods while maintaining the ability to drive larger display areas.
2Duration of action of moving object
If the scan driving circuit delay is reduced, then the reset duration is extended, but the display panel size must be limited
Solution Approach 1:
The gate driving circuit employs periodic interlaced scanning where odd rows and even rows are driven in alternating time periods. The first gate register controls odd rows during one time period while the second gate register controls even rows during another time period. This periodic action allows the reset duration for each row to be extended by utilizing the time when other rows are being driven, thereby maintaining adequate reset duration without limiting the overall display area.
3Duration of action of moving object
If the reset duration is extended through interlaced row driving, then the first reset transistor can be fully reset, but the gate driving circuit complexity increases
Solution Approach 1:
Multiple functions are merged into the interlaced gate driving circuit. The same gate driving circuit structure is used to achieve both the extended reset duration and the row-by-row scanning function. The first and second gate registers share the same basic structure and control logic, allowing the circuit to maintain functionality while extending reset duration through the interlaced operating mode rather than requiring completely separate control paths.
Data Source
AI summary
An array substrate includes multiple pixel driving circuits and a first gate driving circuit. Each pixel driving circuit includes a first reset transistor and a threshold compensation transistor. A gate of the first reset transistor is electrically connected to a first reset control terminal, and the control terminal of the threshold compensation transistor is electrically connected to a compensation control terminal. The output terminal of an i-th first gate register is electrically connected to both the compensation control terminal of the pixel driving circuit in the g-th row and the first reset control terminal of the pixel driving circuit in the (g+h)-th row, where h is a positive integer greater than 1. In this manner, the reset duration of the first reset transistor in the pixel driving circuit can be extended to ensure that the first reset transistor can be fully reset.