Interlaced Signal and Shielding Traces for Crosstalk Reduction
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Solution Overview
Problem
The increasing demand for high-speed input/output connections in semiconductor chip packages leads to crosstalk and coupling issues between conductive traces on printed circuit boards, affecting signal quality and integrity.
Innovation Solution
The semiconductor device employs an interlaced arrangement of signal and shielding traces, where shielding traces are coupled to a predetermined voltage to provide a shielding pattern, enhancing signal integrity by minimizing crosstalk and optimizing trace density for different data transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of conductive traces is increased to support more I/O connections, then the functionality and data transmission capacity are improved, but the crosstalk and coupling problems between adjacent traces worsen
Solution Approach 1:
The patent introduces ground traces as intermediary elements positioned between adjacent signal-carrying conductive traces. These ground traces act as mediators that shield the signal traces from each other, reducing electromagnetic coupling and crosstalk. The ground traces are connected to ground potential, creating a reference plane that isolates adjacent signal traces and prevents harmful electromagnetic interference while allowing the PCB to support increased I/O connections.
2Area of stationary object
If the width and spacing of conductive traces are reduced to minimize PCB space, then the area utilization is improved, but the signal integrity and crosstalk resistance deteriorate
Solution Approach 1:
Ground traces are inserted between narrow signal traces to provide shielding without significantly increasing the overall PCB area. The ground traces are positioned strategically to maximize their shielding effect while maintaining compact trace routing, allowing narrow signal traces to be spaced closer together without compromising signal integrity.
Solution Approach 2:
The patent applies different trace configurations locally - signal traces are routed with varying widths and spacing depending on their functional requirements, while ground traces are positioned specifically where crosstalk risk is highest. This localized optimization allows area-efficient routing in some regions while maintaining signal integrity in critical areas through targeted shielding.
3Productivity
If conductive traces are arranged in parallel to transmit address/data bus signals, then the data transmission efficiency is improved, but the crosstalk between adjacent traces increases
Solution Approach 1:
Ground traces are positioned between parallel signal traces carrying address and data bus signals. These intermediary ground traces break the electromagnetic coupling between adjacent signal traces while maintaining the parallel arrangement necessary for efficient bus transmission. The ground traces create isolated channels that prevent crosstalk between different bus lines.
Solution Approach 2:
The parallel trace arrangement is segmented by inserting ground traces between signal traces, dividing the continuous parallel structure into isolated segments. This segmentation maintains the parallel routing efficiency for data transmission while preventing electromagnetic interference between adjacent segments through the grounding barriers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves signal integrity and transmission performance, particularly in high-speed applications, while ensuring compatibility with various generations of memory devices, thus enhancing forward and backward compatibility.
Implementation Method 1
a plurality of shielding traces (190 2 , 190 4 , 190 6 ) coupled to a predetermined voltage for providing a shielding pattern
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.