Interlayer Buffer Structure for Thicker High-Voltage HEMT Epitaxy
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Solution Overview
Problem
High electron mobility transistor (HEMT) devices face issues with tensile stress and cracking due to lattice mismatch and thermal expansion during fabrication, limiting the thickness of the epitaxial stack and reducing the soft breakdown voltage.
Innovation Solution
Incorporation of interlayer buffer layers formed at a lower temperature between superlattice layers to mitigate tensile stress, allowing for increased thickness and improved crystal quality, thereby reducing cracking and dislocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the epitaxial stack thickness is increased to improve device performance, then the soft breakdown voltage increases, but tensile stress and cracking occur due to lattice mismatch and thermal expansion
Solution Approach 1:
The buffer structure is segmented into multiple functional layers including a graded buffer layer with gradually changing composition, superlattice layers with alternating materials, and interlayer buffer layers. This segmentation allows each layer to manage stress differently, preventing catastrophic cracking while enabling increased total thickness for higher breakdown voltage.
Solution Approach 2:
The composition gradient in the graded buffer layer gradually changes the lattice constant from the substrate to the channel layer, reducing thermal mismatch. The superlattice layers use alternating materials with different properties to manage stress. These parameter changes allow the structure to accommodate thermal expansion differences without cracking, enabling thicker epitaxial stacks.
2Length of moving object
If the epitaxial stack thickness is increased to improve device performance, then the soft breakdown voltage increases, but lattice mismatch causes tensile stress
Solution Approach 1:
The graded buffer layer uses a composition gradient that gradually changes the lattice constant, reducing the abrupt mismatch between substrate and channel layer. This gradual parameter change minimizes tensile stress accumulation, allowing thicker stacks without stress-induced failures.
Solution Approach 2:
The buffer structure employs composite materials including the graded buffer layer with varying composition, superlattice layers with alternating materials, and interlayer buffer layers. This composite approach allows different regions to handle stress differently, reducing overall tensile stress while enabling increased thickness for higher breakdown voltage.
3Ease of manufacture
If conventional buffer structures are used, then fabrication is simpler, but crystal quality deteriorates due to cracking and dislocations
Solution Approach 1:
The buffer structure is divided into multiple specialized layers (graded buffer layer, superlattice layers, interlayer buffer layers) that work together to prevent cracking and dislocations. While more complex than a single-layer buffer, this segmentation can be integrated into existing fabrication processes and significantly improves crystal quality by reducing defects.
Solution Approach 2:
The multi-layer composite buffer structure uses materials with gradually changing properties to manage stress and improve crystal quality. The graded composition and alternating superlattice structures can be deposited using standard epitaxial growth techniques, making the solution compatible with existing fabrication while dramatically reducing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The interlayer buffer layers enhance the overall performance and reliability of the high voltage device by maintaining compressive force and minimizing tensile stress, enabling an increased epitaxial stack thickness without compromising crystal quality.
Implementation Method 1
the interlayer buffer layers are formed at a second temperature less than the first temperature and are configured to reduce tensile stress in the first superlattice layer and/or the channel layer
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channel layer overlies the plurality of superlattice layers. An active layer overlies the channel layer. A first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. The first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.